search for: cmovb

Displaying 9 results from an estimated 9 matches for "cmovb".

Did you mean: movb
2004 Sep 10
2
An assembly optimization and fix
..._3 - movq mm3, mm0 ; mm3 = total_error_1:total_error_0 - psrlq mm3, 32 ; mm3 = 0:total_error_1 - movd ebx, mm0 ; ebx = total_error_0 movd ecx, mm3 ; ecx = total_error_1 - emms - mov eax, ebx ; eax = total_error_0 - cmp ecx, ebx + + xor ebx, ebx + xor ebp, ebp + inc ebx + cmp ecx, eax cmovb eax, ecx ; eax = min(total_error_0, total_error_1) + cmovbe ebp, ebx + inc ebx cmp edx, eax cmovb eax, edx ; eax = min(total_error_0, total_error_1, total_error_2) + cmovbe ebp, ebx + inc ebx cmp esi, eax cmovb eax, esi ; eax = min(total_error_0, total_error_1, total_error_2, total_er...
2015 Jan 22
2
[LLVMdev] X86TargetLowering::LowerToBT
> On Jan 22, 2015, at 1:22 PM, Fiona Glaser <fglaser at apple.com> wrote: > > According to Agner’s docs, many CPUs have slower BT than TEST; Haswell has only 0.5 inverse throughput as opposed to 0.25, Atom has 1 instead of 0.5, and Silvermont can’t even dual-issue BT (it locks both ALUs). So while BT does seem have a shorter instruction encoding than TEST for TEST reg, imm32 where
2017 Apr 19
3
[cfe-dev] FE_INEXACT being set for an exact conversion from float to unsigned long long
...t; movss LCPI1_0(%rip), %xmm1 > cvttss2siq %xmm0, %rcx > movaps %xmm0, %xmm2 > subss %xmm1, %xmm2 > cvttss2siq %xmm2, %rax > movabsq $-9223372036854775808, %rdx > xorq %rdx, %rax > ucomiss %xmm1, %xmm0 > cmovb %rcx, %rax > ret > > >> On 19 Apr 2017, at 2:10 PM, Michael Clark <michaeljclark at mac.com <mailto:michaeljclark at mac.com>> wrote: >> >> >>> On 19 Apr 2017, at 1:14 PM, Tim Northover <t.p.northover at gmail.com <mailto:t.p.northov...
2015 Jan 22
2
[LLVMdev] X86TargetLowering::LowerToBT
...<chris.sears at gmail.com> wrote: > > I think the partial update issue isn't really valid concern, Agner Fogg, p 142. I don't think LLVM is going to emit this fragment. > > ; Example 10.7. Partial register access > bt eax,2 ; modifies carry flag but not zero flag > cmovbe eax,ebx ; reads both carry flag and zero flag > > In cases like this, you may consider whether it is a programming error or a deliberate testing of two different conditions with a single instruction. > _______________________________________________ > LLVM Developers mailing list >...
2012 Mar 02
3
[LLVMdev] Access Violation using ExecutionEngine on 64-bit Windows 8 Consumer Preview
...with Windows 7) is: 00000000773A0DD0 sub rsp,10h 00000000773A0DD4 mov qword ptr [rsp],r10 00000000773A0DD8 mov qword ptr [rsp+8],r11 00000000773A0DDD xor r11,r11 00000000773A0DE0 lea r10,[rsp+18h] 00000000773A0DE5 sub r10,rax 00000000773A0DE8 cmovb r10,r11 00000000773A0DEC mov r11,qword ptr gs:[10h] 00000000773A0DF5 cmp r10,r11 00000000773A0DF8 jae 00000000773A0E10 00000000773A0DFA and r10w,0F000h 00000000773A0E00 lea r11,[r11-1000h] 00000000773A0E07 mov byte ptr [r11],0 00000000773A...
2012 Feb 14
0
[LLVMdev] Strange behaviour with x86-64 windows, bad call instruction address
...word ptr [rax+rax] 0000000077B3F1D0 sub rsp,10h 0000000077B3F1D4 mov qword ptr [rsp],r10 0000000077B3F1D8 mov qword ptr [rsp+8],r11 0000000077B3F1DD xor r11,r11 0000000077B3F1E0 lea r10,[rsp+18h] 0000000077B3F1E5 sub r10,rax 0000000077B3F1E8 cmovb r10,r11 0000000077B3F1EC mov r11,qword ptr gs:[10h] 0000000077B3F1F5 cmp r10,r11 0000000077B3F1F8 jae 0000000077B3F210 0000000077B3F1FA and r10w,0F000h 0000000077B3F200 lea r11,[r11-1000h] 0000000077B3F207 mov byte ptr [r11],0 0000000077B3...
2017 Apr 20
4
[cfe-dev] FE_INEXACT being set for an exact conversion from float to unsigned long long
...%rdx, %rax ret instead of _conv: movss LCPI1_0(%rip), %xmm1 cvttss2siq %xmm0, %rcx movaps %xmm0, %xmm2 subss %xmm1, %xmm2 cvttss2siq %xmm2, %rax movabsq $-9223372036854775808, %rdx xorq %rdx, %rax ucomiss %xmm1, %xmm0 cmovb %rcx, %rax ret On 19 Apr 2017, at 2:10 PM, Michael Clark <michaeljclark at mac.com<mailto:michaeljclark at mac.com>> wrote: On 19 Apr 2017, at 1:14 PM, Tim Northover <t.p.northover at gmail.com<mailto:t.p.northover at gmail.com>> wrote: On 18 April 2017 at 15:54,...
2012 Feb 21
0
[LLVMdev] Strange behaviour with x86-64 windows, bad call instruction address
...word ptr [rax+rax] 0000000077B3F1D0 sub rsp,10h 0000000077B3F1D4 mov qword ptr [rsp],r10 0000000077B3F1D8 mov qword ptr [rsp+8],r11 0000000077B3F1DD xor r11,r11 0000000077B3F1E0 lea r10,[rsp+18h] 0000000077B3F1E5 sub r10,rax 0000000077B3F1E8 cmovb r10,r11 0000000077B3F1EC mov r11,qword ptr gs:[10h] 0000000077B3F1F5 cmp r10,r11 0000000077B3F1F8 jae 0000000077B3F210 0000000077B3F1FA and r10w,0F000h 0000000077B3F200 lea r11,[r11-1000h] 0000000077B3F207 mov byte ptr [r11],0 0000000077B3...
2017 Apr 21
2
[cfe-dev] FE_INEXACT being set for an exact conversion from float to unsigned long long
...%rdx, %rax ret instead of _conv: movss LCPI1_0(%rip), %xmm1 cvttss2siq %xmm0, %rcx movaps %xmm0, %xmm2 subss %xmm1, %xmm2 cvttss2siq %xmm2, %rax movabsq $-9223372036854775808, %rdx xorq %rdx, %rax ucomiss %xmm1, %xmm0 cmovb %rcx, %rax ret On 19 Apr 2017, at 2:10 PM, Michael Clark <michaeljclark at mac.com<mailto:michaeljclark at mac.com>> wrote: On 19 Apr 2017, at 1:14 PM, Tim Northover <t.p.northover at gmail.com<mailto:t.p.northover at gmail.com>> wrote: On 18 April 2017 at 15:54,...