search for: clrex

Hi, I was compiling libc++ with a recent TOT (248571) and when I got to the ARMv6, I got a code generation error in memory.cpp: fatal error: error in backend: Cannot select: intrinsic %llvm.arm.clrex ecc: error: clang frontend command failed with exit code 70 (use -v to see invocation) clang version 3.8.0 (trunk) It looks as if the newly added emitAtomicCmpXchgNoStoreLLBalance() function is the culprit. Does this seem like a resaonable fix, or do I need to do something different for v6 and...

...<llvm-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I was compiling libc++ with a recent TOT (248571) and when I got to the >> ARMv6, I got a code generation error in memory.cpp: >> >> fatal error: error in backend: Cannot select: intrinsic %llvm.arm.clrex >> ecc: error: clang frontend command failed with exit code 70 (use -v to see >> invocation) >> clang version 3.8.0 (trunk) >> >> It looks as if the newly added emitAtomicCmpXchgNoStoreLLBalance() >> function is the culprit. Does this seem like a resaonable fix,...

...:pair<unsigned int, unsigned int> llvm::CGIOperandList::getSubOperandNumber(unsigned int) const: Assertion `i < OperandList.size() && "Invalid flat operand #"' failed.* How can I define an instruction with no operand? In ARM there is a similar instruction like "CLREX" but I don't understand why in the assertion in CodeGenInstruction.h number of sub operand num should be more than 0? getSubOperandNumber counts the operator (i.e. the instruction mnemonic itself) as well? I mean, we will have minimum 1 in any situation or it's just the number of opera...

On 11/6/2015 11:35 AM, Sky Flyer via llvm-dev wrote: > Guys, I stuck at this point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr,

...w8, w1 b.ne .LBB0_3 // BB#1: // %cmpxchg.trystore stlxr w8, w2, [x0] cbz w8, .LBB0_4 // BB#2: // %cmpxchg.failure mov w0, wzr ret .LBB0_3: // %cmpxchg.nostore clrex mov w0, wzr ret .LBB0_4: orr w0, wzr, #0x1 ret GCC instead generates a ldaxr for the initial load, which seems more correct to me since it is honoring the requested failure case acquire ordering. I'd like to get other opinions on this before filing a bug. I belie...

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See