search for: clock

....c:ads_add_machine_acct(1405) ads_add_machine_acct: Host account for mustang already exists - modifying old account [2006/08/23 19:45:00, 0] libads/kerberos.c:get_service_ticket(337) get_service_ticket: kerberos_kinit_password MUSTANG$@MACHINEVISIONPRODUCTS.COM@MACHINEVISIONPRODUCTS.COM failed: Clock skew too great [2006/08/23 19:45:00, 0] libads/kerberos.c:get_service_ticket(337) get_service_ticket: kerberos_kinit_password MUSTANG$@MACHINEVISIONPRODUCTS.COM@MACHINEVISIONPRODUCTS.COM failed: Clock skew too great [2006/08/23 19:45:00, 0] libads/kerberos.c:get_service_ticket(337) get_service_...

While I've not reviewed the patch in too much detail, it looks promising. Can you run some end-to-end benchmarks to make sure that cache pressure in the full program or other variables not accounted for in a micro-benchmark don't dominate performance? Specifically the nightly tester includes a number of real programs and machinery to measure total compile time. On Sat, Feb 6, 2010 at 7:09

Adds a NvReclock boolean option to allow the user to enable (or disable) reclocking. All chipsets default to off, except NVAA/NVAC, which are reportedly complete. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Ben, I know you've been saying that reclocking is in a pretty bad state, but I do th...

Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved. These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a r...

While I thought I had this correct (since it actually did reject modes like I expected during testing), Ville Syrjala from Intel pointed out that the logic here isn't correct. max_clock refers to the max symbol rate supported by the encoder, so limiting clock to ds_clock using max() doesn't make sense. Additionally, we want to check against 6bpc for the time being since that's the minimum possible bpc here, not the reported bpc from the connector. See: https://lists.freed...

...Ville Syrj?l? wrote: > On Tue, Sep 22, 2020 at 05:05:10PM -0400, Lyude Paul wrote: > > While I thought I had this correct (since it actually did reject modes > > like I expected during testing), Ville Syrjala from Intel pointed out > > that the logic here isn't correct. max_clock refers to the max symbol > > rate supported by the encoder, so limiting clock to ds_clock using max() > > doesn't make sense. Additionally, we want to check against 6bpc for the > > time being since that's the minimum possible bpc here, not the reported > > bpc from...

...ance? Specifically the > nightly tester includes a number of real programs and machinery to > measure total compile time. Ok, now with some kinda-hard numbers! murmurhash2 | superfasthash | - 6.6404 seconds (6.6697 wall clock) | 6.6204 seconds (6.8557 wall clock) + 2.6722 seconds (2.7064 wall clock) | 2.7962 seconds (2.7502 wall clock) + 8.6725 seconds (8.6662 wall clock) | 8.7526 seconds (8.7162 wall clock) + 2.7362 seconds (2.7729 wall clock) | 2.8242 seconds (2.8146 wall clock) + 1.4281 seconds (1.4068 wall clock) |...

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wr...

...els[] = { > > >>> .vsync_start = 240 + 5, > > >>> .vsync_end = 240 + 5 + 6, > > >>> .vtotal = 240 + 5 + 6 + 5, > > >>> - .vrefresh = 116, > > >> > > >> Are you sure vrefresh calculated (from totals and clock) is different > > >> than this field? If not, we risk regressions. > > >> > > >> This case is OK, but there is plenty other cases. > > > IIRC I did spot check a few of them. But which code exactly do you think > > > is abusing vrefresh and thus...

...atile_panel_type versatile_panels[] = { > >>> .vsync_start = 240 + 5, > >>> .vsync_end = 240 + 5 + 6, > >>> .vtotal = 240 + 5 + 6 + 5, > >>> - .vrefresh = 116, > >> > >> Are you sure vrefresh calculated (from totals and clock) is different > >> than this field? If not, we risk regressions. > >> > >> This case is OK, but there is plenty other cases. > > IIRC I did spot check a few of them. But which code exactly do you think > > is abusing vrefresh and thus could break? > >...

The time appears to be perfect inside dom0, however all the domU''s tend to have a slightly faster date which gets further out of sync every day. I''m currently using Xen 3.0.3 with Gentoo Linux, under 3.0.2 I had no problems with domU clocks. Are there any known issues which could cause this? I''d strongly prefer not to run ntpd in every domU, having all domU clocks in sync with dom0 is quite important for me. _______________________________________________ Xen-users mailing list Xen-users@lists.xensource.com http://lists....

Some additional info can be found at: http://murmurhash.googlepages.com/ http://en.wikipedia.org/wiki/MurmurHash http://www.codeproject.com/KB/recipes/hash_functions.aspx as well as in the patch description itself. Patch and benchmark attached. Gregory -------------- next part -------------- A non-text attachment was scrubbed... Name:

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Hope I understood you correctly wrt the mem exec stuff. nvkm/subdev/fb/ramnv50.c | 2 +- nvkm/subdev/fb/ramnva3.c | 2 +- nvkm/subdev/fb/ramnvc0.c | 2 +- nvkm/subdev/fb/ramnve0.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/nvkm/subdev/fb/ramnv50.c b/nvkm/subdev/fb/ramnv50.c index ef91b6e..e5d12c2 100644

On 17 May 2014 02:43, "Ilia Mirkin" <imirkin at alum.mit.edu> wrote: > > Adds a NvReclock boolean option to allow the user to enable (or disable) > reclocking. All chipsets default to off, except NVAA/NVAC, which are > reportedly complete. Hey Ilia, I think I've expressed my thoughts on this previously via IRC, but let me stick them here too so there's a record of the cur...

Just a backport of the two patches for v5.9 that you'll want to apply. The first one was Cc'd to stable, but I forgot to Cc the second one as well. Lyude Paul (2): drm/nouveau/kms/nv50-: Get rid of bogus nouveau_conn_mode_valid() drm/nouveau/kms/nv50-: Fix clock checking algorithm in nv50_dp_mode_valid() drivers/gpu/drm/nouveau/nouveau_connector.c | 36 ++++++--------------- drivers/gpu/drm/nouveau/nouveau_dp.c | 21 ++++++++---- 2 files changed, 24 insertions(+), 33 deletions(-) -- 2.28.0

...-- perhaps it'll > like that mode better. Using "-r 75" fixes the problem. > Also does 720x480 work better? Yes, 720x480 works without the -r parameter. > Looking at your EDID, you have: > > Established timings supported: > 720x400 at 70Hz 9:5 HorFreq: 31469 Hz Clock: 28.320 MHz > 640x480 at 60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz > 640x480 at 75Hz 4:3 HorFreq: 37500 Hz Clock: 31.500 MHz > 800x600 at 60Hz 4:3 HorFreq: 37900 Hz Clock: 40.000 MHz > 800x600 at 75Hz 4:3 HorFreq: 46900 Hz Clock: 49.500 MHz > 1024x768 at 60Hz 4:3 HorFreq...

...as well, whoops. While I don't think anyone's likely using 3D output with nouveau, the next patch will make nouveau_conn_mode_valid() make a lot less sense. So, let's just get rid of it and open-code it like before, while taking care to move the 3D frame packing calculations on the dot clock into the right place. Signed-off-by: Lyude Paul <lyude at redhat.com> Fixes: d6a9efece724 ("drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST") Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: <stable at vger.kernel.org> # v5.8+ --- drivers/gpu...

...y the dependencies between domains in DT? > > I think the dependencies could be in the driver. Of course the power > domains are per-SoC data, so really shouldn't be in the DTS either (the > data is all implied by the compatible value) but there's no good way to > get at the clocks and resets without DT, so I think that's a reasonable > trade-off. > > It seems to me like there are only two dependencies: > > DIS and DISB depend on SOR > VE depends on DIS > > That's according to 5.6.6 "Programming Guide for Power Gating and > Ungati...

Hi List, After reading a bunch of the docs, list post archives, it still seems that a clear definition of how to clock the T100P card is muddy. zttool says that the link is "INTERNALLY CLOCKED", does this mean the T100P is providing clock, or does this mean the T100P is getting clock from the T1 line side (ergo getting clock from the Telco) ?? If you have sync = 0 then zttool says internally clocke...

...5 range: (0, 15) Backlight: 15 range: (0, 15) scaling mode: Full aspect supported: NoneFullCenterFull aspect 1920x1080 (0x96) 139.0MHz -HSync -VSync *current +preferred h: width 1920 start 1980 end 2028 total 2050 skew 0 clock 67.8KHz v: height 1080 start 1090 end 1100 total 1130 clock 60.0Hz 1920x1080 (0xf5) 138.5MHz +HSync -VSync h: width 1920 start 1968 end 2000 total 2080 skew 0 clock 66.6KHz v: height 1080 start 1083 end 1088 total 1111 clock 59.9Hz 1920x1...