search for: clobber

...k I have run into another CachingMemorySSAWalker cache bug. It's a bit tricky to reproduce, so I'd like to start by trying to show you what is happening when running EarlyCSE with my local changes to use MemorySSA. I've attached a debug log that shows that the value returned by getClobberingMemoryAccess(Inst) after a call to removeMemoryAccess is wrong. The MemorySSA node in question is MemoryUse(7), and the corruption happens after a call to remove MemoryUse(2), at which point its clobber value changes to '1 = MemoryDef(liveOnEntry)'. The interesting thing is that is...

There is no need any longer to store the clobbers in struct paravirt_patch_site. Remove clobbers from the struct and from the related macros. While at it fix some lines longer than 80 characters. Signed-off-by: Juergen Gross <jgross at suse.com> --- arch/x86/include/asm/paravirt.h | 33 +++++++++++++++------------------ arch/x86/in...

...include/asm/paravirt-asm.h b/arch/x86/include/asm/paravirt-asm.h index add8a190fdac..8bdd50ee4bf3 100644 --- a/arch/x86/include/asm/paravirt-asm.h +++ b/arch/x86/include/asm/paravirt-asm.h @@ -7,16 +7,18 @@ #include <asm/asm.h> #include <asm/paravirt_types.h> -#define _PVSITE(ptype, clobbers, ops, word, algn) \ -771:; \ - ops; \ -772:; \ - .pushsection .parainstructions,"a"; \ - .align algn; \ - word 771b; \ - .byte ptype; \ - .byte 772b-771b; \ - .short clobbers; \ +#define PV_TYPE(ops, off) ((PARAVIRT_PATCH_##ops + (off)) / __ASM_SEL(4, 8))...

...%1; call *%0\n\t" "popl %1; popl %%edx; popl %%ecx", PARAVIRT_RESTORE_FLAGS) : : "m" (paravirt_ops.restore_fl), "a"(f) : "memory"); } Wouldn't adding ecx/edx (and maybe eax, where it has no other use) to the asm's clobber list be sufficient? This also has the nice effect of making these registers are freely available for inlined code to use as temps, and making the register usage match the normal ABI calling convention. On the other hand, I suppose, if the inlined code doesn't need the registers, it is a wa...

The clobbers parameter from paravirt_patch_default() et al isn't used any longer. Remove it. Signed-off-by: Juergen Gross <jgross at suse.com> --- arch/x86/include/asm/paravirt_types.h | 7 +++---- arch/x86/kernel/alternative.c | 2 +- arch/x86/kernel/paravirt.c | 14 +++++-----...

...000..add8a190fdac --- /dev/null +++ b/arch/x86/include/asm/paravirt-asm.h @@ -0,0 +1,126 @@ +#ifndef _ASM_X86_PARAVIRT_ASM_H +#define _ASM_X86_PARAVIRT_ASM_H + +#ifdef CONFIG_PARAVIRT +#ifdef __ASSEMBLY__ + +#include <asm/asm.h> +#include <asm/paravirt_types.h> + +#define _PVSITE(ptype, clobbers, ops, word, algn) \ +771:; \ + ops; \ +772:; \ + .pushsection .parainstructions,"a"; \ + .align algn; \ + word 771b; \ + .byte ptype; \ + .byte 772b-771b; \ + .short clobbers; \ + .popsection + + +#define COND_PUSH(set, mask, reg) \ + .if ((~(set)) &...

On 1/8/2013 3:52 PM, Eli Friedman wrote: > > From gcc docs: "If your assembler instructions access memory in an > unpredictable fashion, add `memory' to the list of clobbered > registers. This causes GCC to not keep memory values cached in > registers across the assembler instruction and not optimize stores or > loads to that memory. You also should add the volatile keyword if the > memory affected is not listed in the inputs or outputs of the asm, as >...

...#39;'>Content</tag1> #=> { "tag1" => "Content" } - I think it should return - {"tag1" => { "attr1" => ''1'', "__content__" => "Content" } 2. Mixed content can throw an error or get clobbered - <tag1>Content <em>is</em> Clobbered</tag1> #=> Raises a Private error called on array gsub - <tag1>Content <em>is</em></tag1> #=> Clobbered. Returns {"tag1"=>"Content "} - Feels like it s...

Hi all, I'm tracking down a register allocation problem and I'm trying to understand this piece of code in InlineSpiller::spillAroundUses: // Find the slot index where this instruction reads and writes OldLI. // This is usually the def slot, except for tied early clobbers. SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot(); if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true))) if (SlotIndex::isSameInstr(Idx, VNI->def)) Idx = VNI->def; Comments in SlotIndexes.h have this to say: /// Early-clobber register use/def slot....

Using Clang/LLVM 3.6.0 we are observing a case where the optimizations are clobbering EFLAGS on x86_64. This is inconvenient when the status of bit 9 (IF), which controls interrupts, changes. Here's a simple test program. Assume that the external function foo() modifies the IF bit in EFLAGS. --- #include <stdlib.h> #include <stdbool.h> void foo(void); int...

On Oct 19, 2010, at 8:00 PM, Jakob Stoklund Olesen wrote: > > > One problem is that calling conventions are handled while building the selection DAG, and the DAG doesn't really know to represent clobbered registers. > > Perhaps X86TargetLowering::LowerCall() could decorate the X86ISD::CALL node with the calling convention somehow? > > Dan, do you have any thoughts on how to communicate the calling convention and call clobbered registers to the eventual CALL MachineInstr? The simples...

Consider this program: --- asm.c --- int G; int foo(char *p) { int rv; G = 0; asm ("" : "=r"(rv) : "r"(p) : "memory"); return rv + G; } ------------- Is the use of "memory" clobber sufficient to expect the optimizer not to optimize the "+ G" away in the return statement? I'll add here that currently it does get eliminated. This happens because in TargetLowering::getConstraintType we don't recognize the string "memory" as a memory clobber, but...

...dule. IPRA's scope is limited to a module so for such externally defined function it uses default calling convention but here as the function is written in assembly user can provide exact register usage detials. So we dicided to mark declration of such function with __attribute__((regmask("clobbered list here"))) so LLVM can construct regmask out of it and use it with IPRA to improve register allocation. For this purpose I added support for this attribute in clang and clang codegen this attribute as target dependent attribute and add to declaration. Then IPRA constructs regmask from th...

Hi all, I am currently working on AMDGPU inline assembly and encountered problem with naming clobber registers in asm constraints. It looks like by default LLVM tries to match register specified in constraint to register name of register definition in .td file but not to the AsmName for this register. For example if we have register definition: def MYReg0 : Register<"r0", 0>; W...

...uld never emit pushf / popf. I'm not sure this patch to fix it ever got committed: http://reviews.llvm.org/D6629 On Wed, Jul 29, 2015 at 3:11 PM, Michael Hordijk <hoffbrinkle at hotmail.com> wrote: > > Using Clang/LLVM 3.6.0 we are observing a case where the optimizations are > clobbering EFLAGS on x86_64. This is inconvenient when the status of bit 9 > (IF), which controls interrupts, changes. > > Here's a simple test program. Assume that the external function foo() > modifies the IF bit in EFLAGS. > > --- > > #include <stdlib.h> > #include...

...ue, Jan 8, 2013 at 2:17 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > On 1/8/2013 3:52 PM, Eli Friedman wrote: >> >> >> From gcc docs: "If your assembler instructions access memory in an >> unpredictable fashion, add `memory' to the list of clobbered >> registers. This causes GCC to not keep memory values cached in >> registers across the assembler instruction and not optimize stores or >> loads to that memory. You also should add the volatile keyword if the >> memory affected is not listed in the inputs or outputs of...

...quot;edx"); printf("data[0] = %x \n",data[0]); printf("data[1] = %x \n",data[1]); printf("data[2] = %x \n",data[2]); printf("data[3] = %x \n",data[3]); return 0; } In this case the value of data[0] has got corrupted as clang is not honoring clobbered register and stores a different value in $eax. Similarly when compiled with -fPIE option, GCC emits an error as - i386-pseudo.c: In function ‘main’: i386-pseudo.c:13:3: error: PIC register clobbered by ‘ebx’ in ‘asm’ i386-pseudo.c:22:3: error: PIC register clobbered by ‘ebx’ in ‘asm’ Clang co...

...analyzed is: >>>> %BX<def> = MOV16rm %EDI, 2, %ECX, 0, %noreg; >>> mem:LD2[%arrayidx98](tbaa=!18) >>>> >>>> and the Reg being passed in is 21, which is EBX. The result I get back for >>> is: >>>> >>>> Analysis: {Clobbers = true, Defines = true, Reads = false, ReadsOverlap = >>> false, >>>> DefinesDead = false, Kills = false} >>>> >>>> It seems based on the comment in the definition of PhysRegInfo.Defines, >>> that Defines should only be true if Reg or a super-...

...the instructions in the middle (ii): 1. A verbatim translation into an 'add' and a 'sub' instruction. I prefer this because it does not modify the flags in question. 2. The more idiomatic translation into 'negadd'. In this context, this translation is incorrect because it clobbers the flag and disrupts the data dependence from (i) to (iii). How can I specify that the second choice is incorrect in this instance because it clobbers the implicit flow. Thank you, Nick Johnson D. E. Shaw Research

...ps; extern struct pv_lock_ops pv_lock_ops; -#define PARAVIRT_PATCH(x) \ - (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) - -#define paravirt_type(op) \ - [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \ - [paravirt_opptr] "i" (&(op)) -#define paravirt_clobber(clobber) \ - [paravirt_clobber] "i" (clobber) - -/* - * Generate some code, and mark it as patchable by the - * apply_paravirt() alternate instruction patcher. - */ -#define _paravirt_alt(insn_string, type, clobber) \ - "771:\n\t" insn_string "\n" "772:\n"...