Displaying 13 results from an estimated 13 matches for "clks".
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clk
2016 Aug 26
0
[PATCH v8 01/18] remoteproc: st_slim_rproc: add a slimcore rproc driver
...+static const char *mem_names[ST_SLIM_MEM_MAX] = {
+ [ST_SLIM_DMEM] = "dmem",
+ [ST_SLIM_IMEM] = "imem",
+};
+
+static int slim_clk_get(struct st_slim_rproc *slim_rproc, struct device *dev)
+{
+ int clk, err;
+
+ for (clk = 0; clk < ST_SLIM_MAX_CLK; clk++) {
+ slim_rproc->clks[clk] = of_clk_get(dev->of_node, clk);
+ if (IS_ERR(slim_rproc->clks[clk])) {
+ err = PTR_ERR(slim_rproc->clks[clk]);
+ if (err == -EPROBE_DEFER)
+ goto err_put_clks;
+ slim_rproc->clks[clk] = NULL;
+ break;
+ }
+ }
+
+ return 0;
+
+err_put_clks:
+ while (--clk >= 0)
+ c...
2016 Aug 30
4
[PATCH v8 01/18] remoteproc: st_slim_rproc: add a slimcore rproc driver
...> + [ST_SLIM_DMEM] = "dmem",
> + [ST_SLIM_IMEM] = "imem",
> +};
> +
> +static int slim_clk_get(struct st_slim_rproc *slim_rproc, struct device *dev)
> +{
> + int clk, err;
> +
> + for (clk = 0; clk < ST_SLIM_MAX_CLK; clk++) {
> + slim_rproc->clks[clk] = of_clk_get(dev->of_node, clk);
> + if (IS_ERR(slim_rproc->clks[clk])) {
> + err = PTR_ERR(slim_rproc->clks[clk]);
> + if (err == -EPROBE_DEFER)
> + goto err_put_clks;
> + slim_rproc->clks[clk] = NULL;
> + break;
> + }
> + }
> +
> + retur...
2016 Aug 30
4
[PATCH v8 01/18] remoteproc: st_slim_rproc: add a slimcore rproc driver
...> + [ST_SLIM_DMEM] = "dmem",
> + [ST_SLIM_IMEM] = "imem",
> +};
> +
> +static int slim_clk_get(struct st_slim_rproc *slim_rproc, struct device *dev)
> +{
> + int clk, err;
> +
> + for (clk = 0; clk < ST_SLIM_MAX_CLK; clk++) {
> + slim_rproc->clks[clk] = of_clk_get(dev->of_node, clk);
> + if (IS_ERR(slim_rproc->clks[clk])) {
> + err = PTR_ERR(slim_rproc->clks[clk]);
> + if (err == -EPROBE_DEFER)
> + goto err_put_clks;
> + slim_rproc->clks[clk] = NULL;
> + break;
> + }
> + }
> +
> + retur...
2016 Aug 30
0
[PATCH v8 01/18] remoteproc: st_slim_rproc: add a slimcore rproc driver
...t; > + [ST_SLIM_IMEM] = "imem",
> > +};
> > +
> > +static int slim_clk_get(struct st_slim_rproc *slim_rproc, struct device *dev)
> > +{
> > + int clk, err;
> > +
> > + for (clk = 0; clk < ST_SLIM_MAX_CLK; clk++) {
> > + slim_rproc->clks[clk] = of_clk_get(dev->of_node, clk);
> > + if (IS_ERR(slim_rproc->clks[clk])) {
> > + err = PTR_ERR(slim_rproc->clks[clk]);
> > + if (err == -EPROBE_DEFER)
> > + goto err_put_clks;
> > + slim_rproc->clks[clk] = NULL;
> > + break;
> >...
2016 Aug 26
32
[PATCH v8 00/18] Add support for FDMA DMA controller and slim core rproc found on STi chipsets
...PROC user selectable (Bjorn)
- -EPROBE_DEFER if rproc_boot fails when allocating DMA channel (Arnaud / Peter)
- Drop some unnecessary headers (Vinod / Bjorn)
- Change to writel now we have several mappings (Bjorn)
- Remove io_res, rproc, and some unused structure fields / #define (Bjorn)
- put clks in error path, also put clks before rproc_put() (Bjorn)
- Make enum less generic (Bjorn)
- Make slim_rproc_alloc() return a st_slim_rproc reference (Bjorn)
- Alphabetical naming in Kconfig & Makefile (Vinod)
- Add FDMA prefix to REQ_CTRL* (Vinod)
- Print ret on some error paths (Vinod)
-...
2016 Aug 26
32
[PATCH v8 00/18] Add support for FDMA DMA controller and slim core rproc found on STi chipsets
...PROC user selectable (Bjorn)
- -EPROBE_DEFER if rproc_boot fails when allocating DMA channel (Arnaud / Peter)
- Drop some unnecessary headers (Vinod / Bjorn)
- Change to writel now we have several mappings (Bjorn)
- Remove io_res, rproc, and some unused structure fields / #define (Bjorn)
- put clks in error path, also put clks before rproc_put() (Bjorn)
- Make enum less generic (Bjorn)
- Make slim_rproc_alloc() return a st_slim_rproc reference (Bjorn)
- Alphabetical naming in Kconfig & Makefile (Vinod)
- Add FDMA prefix to REQ_CTRL* (Vinod)
- Print ret on some error paths (Vinod)
-...
2011 Aug 15
2
[LLVMdev] Question on instruction itineraries
...detail ?
For example looking at MBlaze target MBlaeSchedule.td I can see something
like
MblazeSchedule.td
...
def IIImul : InstrItinClass;
...
InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
has something similar.
In Mblaze case I can see the result being used the very next cycle
mul *r3*, r6, r5
addik r3,* r3*, 4
similarly for my target (instead of 17 I'm specifying 2 above) and for Mips
I get the same result. Same for loads where I'm...
2011 Aug 16
0
[LLVMdev] Question on instruction itineraries
...ze target MBlaeSchedule.td I can see something
> like
> MblazeSchedule.td
> ...
> def IIImul : InstrItinClass;
> ...
> InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
>
> Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
> has something similar.
Yes.
> In Mblaze case I can see the result being used the very next cycle
> mul r3, r6, r5
> addik r3, r3, 4
> similarly for my target (instead of 17 I'm specifying 2 above) and for Mips
> I get the same result...
2019 Sep 04
1
[RFC PATCH v2] clk: Remove BYPASS_PLL_CHECK from PLLs
...ut seemed it
wasn't used nowhere for CLK settings.
Removing this works fine, but I don't know what it's really for.
Actual bit setting this BYPASS_PLL_CHECK is on 0x10:
lookup -ac0 0x137000 0x10
PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 }
Also, disabling this bit on other CLKs doesn't seem to break anything.
v2: Add back PLL lock test
Signed-off-by: Mark Menzynski <mmenzyns at redhat.com>
---
drm/nouveau/nvkm/subdev/clk/gf100.c | 1 -
drm/nouveau/nvkm/subdev/clk/gk104.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drm/nouveau/nvkm/subdev/clk/gf100.c...
2019 Sep 06
1
[PATCH v3] clk: Restore BYPASS_PLL_CHECK from PLLs
...ut seemed it
wasn't used nowhere for CLK settings.
Removing this works fine, but I don't know what it's really for.
Actual bit setting this BYPASS_PLL_CHECK is on 0x10:
lookup -ac0 0x137000 0x10
PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 }
Also, disabling this bit on other CLKs doesn't seem to break anything.
v2: add back PLL lock test
v3: add restoring original value after PLL lock test
Signed-off-by: Mark Menzynski <mmenzyns at redhat.com>
---
drm/nouveau/nvkm/subdev/clk/gf100.c | 7 +++++--
drm/nouveau/nvkm/subdev/clk/gk104.c | 5 ++++-
2 files changed, 9...
2019 Sep 04
0
[RFC PATCH] clk: Remove BYPASS_PLL_CHECK from PLLs
...ut seemed it
wasn't used nowhere for CLK settings.
Removing this works fine, but I don't know what it's really for.
Actual bit setting this BYPASS_PLL_CHECK is on 0x10:
lookup -ac0 0x137000 0x10
PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 }
Also, disabling this bit on other CLKs doesn't seem to break anything.
Tested with GF119 NVS 310.
Signed-off-by: Mark Menzynski <mmenzyns at redhat.com>
---
drm/nouveau/nvkm/subdev/clk/gf100.c | 8 --------
drm/nouveau/nvkm/subdev/clk/gk104.c | 8 --------
2 files changed, 16 deletions(-)
diff --git a/drm/nouveau/nvkm/subde...
2011 Aug 17
1
[LLVMdev] Question on instruction itineraries
...ething
> > like
> > MblazeSchedule.td
> > ...
> > def IIImul : InstrItinClass;
> > ...
> > InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
> >
> > Does that mean Mul's are expected to have a latency of 17 clks ? Mips
> target
> > has something similar.
>
> Yes.
>
> > In Mblaze case I can see the result being used the very next cycle
> > mul r3, r6, r5
> > addik r3, r3, 4
> > similarly for my target (instead of 17 I'm specifying 2 abo...
2019 Sep 09
0
[PATCH v4] clk: Restore BYPASS_PLL_CHECK from PLLs
...ut seemed it
wasn't used nowhere for CLK settings.
Removing this works fine, but I don't know what it's really for.
Actual bit setting this BYPASS_PLL_CHECK is on 0x10:
lookup -ac0 0x137000 0x10
PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 }
Also, disabling this bit on other CLKs doesn't seem to break anything.
v2: add back PLL lock test
v3: add restoring original value after PLL lock test
v4: read the bit with nvkm_mask
Signed-off-by: Mark Menzynski <mmenzyns at redhat.com>
---
drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++---
drm/nouveau/nvkm/subdev/clk/gk104...