Displaying 3 results from an estimated 3 matches for "clk_khz".
2014 Aug 21
0
[PATCH 2/7] clock/nva3: Set PLL refclk
...lk;
}
- if (!pll)
- return -ERANGE;
break;
}
+ return -ERANGE;
+}
+
+int
+nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
+ struct nva3_clock_info *info)
+{
+ struct nouveau_bios *bios = nouveau_bios(clock);
+ struct nva3_clock_priv *priv = (void *)clock;
+ int clk_khz;
+ struct nvbios_pll limits;
+ int P, N, M, diff;
+ int ret;
+
+ info->pll = 0;
+
+ /* If we can get a within [-2, 3) MHz of a divider, we'll disable the
+ * PLL and use the divider instead. */
+ clk_khz = nva3_clk_info(clock, clk, khz, info);
+ diff = khz - clk_khz;
+ if (!pll || (diff >...
2014 Aug 21
9
NVA3 clock tree improvements
Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved.
These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated
2011 Oct 09
1
(no subject)
Hi,
This is my work in documenting EVO.
I did some RE to fill missing gaps.
Best regards,
Maxim Levitsky