search for: clk_get_rat

...r. :) I honestly don't mind at all if you completely ignore the non-DRM build and leave it to me to fix up. I personally use the userspace build quite a lot for dev/testing, but don't at all expect others to, or to maintain it. But thank you for bothering :) In any case, it was *almost* (clk_get_rate() was missing) fine. I left a patch in the tree of what I changed, and I'll squash it before it goes to -staging. Thanks again, Ben. > > Alexandre Courbot (3): > clk: make therm and volt devices optional > clk: support for non-BIOS pstates > gk20a: reclocking support &g...

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

..._show_pxlclock(struct seq_file *m, void *arg) { - struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_info_node *node = m->private; struct drm_device *drm = node->minor->dev; struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm); unsigned long clkrate = clk_get_rate(arcpgu->clk); diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 7333f7a87a2f..540faabcf8a4 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -727,9 +727,8 @@ ttm_kmap_iter_linear_io_fini(struct ttm_kmap_iter_line...

..._show_pxlclock(struct seq_file *m, void *arg) { - struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_info_node *node = m->private; struct drm_device *drm = node->minor->dev; struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm); unsigned long clkrate = clk_get_rate(arcpgu->clk); diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 7333f7a87a2f..540faabcf8a4 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -727,9 +727,8 @@ ttm_kmap_iter_linear_io_fini(struct ttm_kmap_iter_line...

...void *arg) > { > - struct drm_info_node *node = (struct drm_info_node *)m->private; > + struct drm_info_node *node = m->private; > struct drm_device *drm = node->minor->dev; > struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm); > unsigned long clkrate = clk_get_rate(arcpgu->clk); > diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c > index 7333f7a87a2f..540faabcf8a4 100644 > --- a/drivers/gpu/drm/ttm/ttm_resource.c > +++ b/drivers/gpu/drm/ttm/ttm_resource.c > @@ -727,9 +727,8 @@ ttm_kmap_iter_linear_io_fini(...

...void *arg) > { > - struct drm_info_node *node = (struct drm_info_node *)m->private; > + struct drm_info_node *node = m->private; > struct drm_device *drm = node->minor->dev; > struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm); > unsigned long clkrate = clk_get_rate(arcpgu->clk); > diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c > index 7333f7a87a2f..540faabcf8a4 100644 > --- a/drivers/gpu/drm/ttm/ttm_resource.c > +++ b/drivers/gpu/drm/ttm/ttm_resource.c > @@ -727,9 +727,8 @@ ttm_kmap_iter_linear_io_fini(...

This series does some refactoring in the GK20A's volt and clk drivers (fixing a few things while we are at it) to let GM20B benefit from the GK20A's logic with which it is compatible. GM20B is capable of more sophisticated (and power-efficient) reclocking which will follow later. Even after this more fancy reclocking is merged, the present logic will remain used in the lowest speedo of

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

...eau_clock_create(parent, engine, oclass, gk20a_domains, + gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->params = &gk20a_pllg_params; + + plat = nv_device_to_platform(nv_device(parent)); + priv->parent_rate = clk_get_rate(plat->gpu->clk); + nv_info(priv, "parent clock rate: %ld Mhz\n", priv->parent_rate / MHZ); + + priv->base.read = gk20a_clock_read; + priv->base.calc = gk20a_clock_calc; + priv->base.prog = gk20a_clock_prog; + priv->base.tidy = gk20a_clock_tidy; + + return 0; +} + +st...

some chipset have working engine reclocking, but broken memory reclocking like Fermi. We should for now, add the functionality to allow partly reclocking for those. Allthough this doesn't give as much performance as one might wish, it is till noticeable and may improve performance enough to be noted. Karol Herbst (2): clk: seperate engine and memory reclock toggles clk: allow engine

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

...a_domains, > + gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); > + *pobject = nv_object(priv); > + if (ret) > + return ret; > + > + priv->params = &gk20a_pllg_params; > + > + plat = nv_device_to_platform(nv_device(parent)); > + priv->parent_rate = clk_get_rate(plat->gpu->clk); > + nv_info(priv, "parent clock rate: %ld Mhz\n", priv->parent_rate / MHZ); > + > + priv->base.read = gk20a_clock_read; > + priv->base.calc = gk20a_clock_calc; > + priv->base.prog = gk20a_clock_prog; > + priv->base.tidy = gk20a_cloc...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate