Displaying 3 results from an estimated 3 matches for "clearresourc".
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clearresources
2015 Nov 17
2
DFAPacketzer, Hexagon and bundles with 1 instruction
...IWPacketizerList::endPacket(MachineBasicBlock *MBB,
MachineInstr *MI) {
if (CurrentPacketMIs.size() > 1) {
MachineInstr *MIFirst = CurrentPacketMIs.front();
finalizeBundle(*MBB, MIFirst, MI);
}
CurrentPacketMIs.clear();
ResourceTracker->clearResources();
}
Based on this, it looks like packets with one instruction are not finalized
(finalizeBundle is the one which inserts a BUNDLE instruction). So what
happens with packets that have only 1 instruction? Is there a separate pass
that creates a bundle from a single instruction?
Any help is appre...
2016 Jan 20
2
a bundle with one instruction
...IWPacketizerList::endPacket(MachineBasicBlock *MBB,
MachineInstr *MI) {
if (CurrentPacketMIs.size() > 1) {
MachineInstr *MIFirst = CurrentPacketMIs.front();
finalizeBundle(*MBB, MIFirst, MI);
}
CurrentPacketMIs.clear();
ResourceTracker->clearResources();
}
My initial idea was to simply add a NOP instruction to the
CurrentPacketMIs, but it is proving to be more difficult than I thought.
Would anyone care to help?
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...>> if (CurrentPacketMIs.size()> 1) {
>> MachineInstr *MIFirst = CurrentPacketMIs.front();
>> - finalizeBundle(*MBB, MIFirst, I);
>> + finalizeBundle(*MBB, MIFirst, MI);
>> }
>> CurrentPacketMIs.clear();
>> ResourceTracker->clearResources();
>> @@ -181,31 +157,36 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
>> void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
>> MachineBasicBlock::iterator BeginItr,
>>...