search for: clear_buffers

...nv50_surface.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c @@ -408,9 +408,6 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, PUSH_DATAf(push, color->f[1]); PUSH_DATAf(push, color->f[2]); PUSH_DATAf(push, color->f[3]); - mode = - NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G | - NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A; } if (buffers & PIPE_CLEAR_DEPTH) { @@ -425,12 +422,16 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, mode |= NV50_3D_CLEAR_BUFFERS_S; } - BEGIN_NV04(push, NV50_3D(CLE...

...h, width * data_size); + PUSH_DATA (push, height); + + PUSH_DATA (push, nvc0_format_table[dst_fmt].rt); + PUSH_DATA (push, 1 << 12); + PUSH_DATA (push, 1); + PUSH_DATA (push, 0); + PUSH_DATA (push, 0); + + IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0); + + IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c); + + if (width * height != elements) { + offset += width * height * data_size; + width = elements - width * height; + height = 1; + + BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); + PUSH_DATA (push, width << 16); + PUSH_DATA (push, height <<...

...nv50_surface.c >> @@ -408,9 +408,6 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, >> PUSH_DATAf(push, color->f[1]); >> PUSH_DATAf(push, color->f[2]); >> PUSH_DATAf(push, color->f[3]); >> - mode = >> - NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G | >> - NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A; >> } >> > I'm not sure why you've dropped the mode from above. I'm guessing that > the initial assumption was that if there is a color buffer it must be at > cbuf...

...PUSH_DATA (push, height); + + PUSH_DATA (push, nvc0_format_table[dst_fmt].rt); + PUSH_DATA (push, 1 << 12); + PUSH_DATA (push, 1); + PUSH_DATA (push, 0); + PUSH_DATA (push, 0); + + IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0); + + IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c); + + if (width * height != elements) { + offset += width * height * data_size; + width = elements - width * height; + height = 1; + + BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); + PUSH_DATA (push, width << 16); + PUSH_DATA (...

...um/drivers/nouveau/nv50/nv50_surface.c > @@ -408,9 +408,6 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, > PUSH_DATAf(push, color->f[1]); > PUSH_DATAf(push, color->f[2]); > PUSH_DATAf(push, color->f[3]); > - mode = > - NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G | > - NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A; > } > I'm not sure why you've dropped the mode from above. I'm guessing that the initial assumption was that if there is a color buffer it must be at cbuf[0]. The corrected versi...

...gt; @@ -408,9 +408,6 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, >>> PUSH_DATAf(push, color->f[1]); >>> PUSH_DATAf(push, color->f[2]); >>> PUSH_DATAf(push, color->f[3]); >>> - mode = >>> - NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G | >>> - NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A; >>> } >>> >> I'm not sure why you've dropped the mode from above. I'm guessing that >> the initial assumption was that if there is a color buffer it...

Hi, please review the following patch! Thanks, Tobias Klausmann

...nv50->scissors_dirty |= 1; > + > BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1); > PUSH_DATA (push, 1); > BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5); > @@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe, > (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT)); > } > > - nv50->dirty |= NV50_NEW_FRAMEBUFFER; > + nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR; > } > > static void > @@ -364,6 +372,14 @@ nv50_clear_depth_stencil(struct pipe_context *pipe, > > PUSH_REFN(push, bo, m...

This is needed since commit 9baa45f78b (st/mesa: bind NULL colorbuffers as specified by glDrawBuffers). Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Not sure whether something needs to be done to clear out the old RT_* settings for that index buffer, or if things are cleared out implicitly. Perhaps instead of skipping indices, RT_CONTROL needs to be adjusted with the

...ght); + + PUSH_DATA (push, nvc0_format_table[dst_fmt].rt); + PUSH_DATA (push, 1 << 12); + PUSH_DATA (push, 1); + PUSH_DATA (push, 0); + PUSH_DATA (push, 0); + + BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1); + PUSH_DATA (push, 0); + BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1); + PUSH_DATA (push, 0x3c); + + if (width * height != elements) { + offset += width * height * data_size; + width = elements - width * height; + height = 1; + + BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2); + PUSH_DATA (push, width <&lt...

...ty |= 1; >> + >> BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1); >> PUSH_DATA (push, 1); >> BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5); >> @@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe, >> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT)); >> } >> >> - nv50->dirty |= NV50_NEW_FRAMEBUFFER; >> + nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR; >> } >> >> static void >> @@ -364,6 +372,14 @@ nv50_clear_depth_stencil(struct pipe_context *pipe, >>...

OK, so there's a bunch of stuff in here. The geometry stuff is based on the work started by Bryan Cain and Christoph Bumiller. Patches 01-12: Add support for geometry shaders and fix related issues Patches 13-14: Make it possible for fb clears to operate on texture attachments with an explicit layer set (as is allowed in gl 3.2). Patches 15-17: Make ARB_texture_multisample work

...c stuff to after state emission It's not too magical, it's used when vertex buffers have been modified, and when you emit an OpenGL fence, for some reason ... - nv50: make use of scissor enable/disable method This isn't actually scissors but a VIEWPORT_HORIZ/VERT, it doesn't affect CLEAR_BUFFERS. VIEWPORT_HORIZ/VERT is scissors, and you can't turn that off. The blob never turns off 0xe00. - nv50: the whole vertex emission rewrite ... I've never seen any indication that index emission has to be split in some way if you have to use multiple push buffers. But I suspect you'll use...

Hi. I've ever wondered how nuch timeis left to timeout while waiting at the boot prompt, so I've writen this small patch to show it. This add a configuration command 'showtimeout'. If you like the patch I could improve it (for example to show the timeout in decimal because now it uses the writehex functions) Regards. -- ______ ________ / / \/ /___ ) I N T E G

...entry=-1, y0=y0 at entry=-1, x1=x1 at entry=0.00885415077, y1=y1 at entry=1, z=1, s0=s0 at entry=0, t0=t0 at entry=0, s1=s1 at entry=0, t1=t1 at entry=0, color=color at entry=0x1dc781c, num_instances=num_instances at entry=1) at state_tracker/st_draw.c:489 #9 0x00007f5be03b2087 in clear_with_quad (clear_buffers=<optimized out>, ctx=0x1dc5d60) at state_tracker/st_cb_clear.c:297 #10 0x00007f5be03b2087 in st_Clear (ctx=0x1dc5d60, mask=16) at state_tracker/st_cb_clear.c:475 #11 0x00007f5bf0310811 in _cogl_framebuffer_gl_clear (framebuffer=0x1ee3000, buffers=<optimized out>, red=<optimized out&g...

This patchset applies some minor fixes to renouveau.xml and then unifies the nv30 and nv40 register definitions. nv30 and nv40 are very similar and have the same offsets for the registers they share. The major differences are: 1. Texture setup is different due to full NPOT support on nv40 2. More advanced blending/render targets on nv40 3. NV30 has fixed function registers, which NV40 lacks The

...be linear */ + pipe_mutex_lock(nv50->screen->base.push_mutex); + if (clear_flags & PIPE_CLEAR_DEPTH) { BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1); PUSH_DATAf(push, depth); @@ -388,8 +401,10 @@ nv50_clear_depth_stencil(struct pipe_context *pipe, mode |= NV50_3D_CLEAR_BUFFERS_S; } - if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0)) + if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0)) { + pipe_mutex_unlock(nv50->screen->base.push_mutex); return; + } PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR); @@ -436,6 +45...

Hi, as it was already discussed on this list, here it is my attempt in splitting virt-p2v in an own repository. Sadly there are things that must be copied from libguestfs, as it cannot be avoided. The approach taken was to run a script (will send separately) to just get the "p2v" subdirectory with its history as own repository, and then add in few followup commits all the bits needed

...pipe_context *pipe, IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0); /* tiled textures don't have to be fenced, they're not mapped directly */ - nvc0_resource_fence(res, NOUVEAU_BO_WR); + nvc0_resource_fence(nvc0, res, NOUVEAU_BO_WR); } BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth); @@ -479,8 +479,8 @@ nvc0_clear_buffer(struct pipe_context *pipe, IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c); } - nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence); - nouveau_fence_ref(nvc0->screen->base.fence.current, &buf-...

Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- src/gallium/drivers/nouveau/nouveau_fence.c | 76 ++++++++++++------------- src/gallium/drivers/nouveau/nouveau_fence.h | 22 +++++-- src/gallium/drivers/nouveau/nouveau_screen.c | 9 +++ src/gallium/drivers/nouveau/nouveau_screen.h | 14 ++--- src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 +-