search for: classses

Displaying 20 results from an estimated 20 matches for "classses".

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2007 Jan 26
7
How to protect attributes from being updated?
Hi! I''m new to Rails! Rails rox! 1 quesion so far: I have :email attribute in User model. I dont'' want :email to allow to be updated. How do i do this with Rails? Do I have to implement required validation manually? Thanks! --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Ruby on Rails:
2012 May 09
2
[LLVMdev] instructions requiring specific physical registers for operands
On May 9, 2012, at 4:27 AM, Anton Korobeynikov wrote: > Hello Jonas, > >> I wonder, what would be the best solution for instructions that require >> operands in a particular register, and even gives the result in a particular >> register? > You need to custom select such instruction. See e.g. div / idiv on x86 > as an example. That's often easiest, yes;
2008 Jul 23
5
Histogram
Hi, how can I treat data organised in classes and frequencies? Ex. class frequency 20-23 9 23-25 7 26-28 5 29-31 5 32-34 3 Thanks Angelo Scozzarella
2009 Apr 02
2
[LLVMdev] JIT compilation and debuggen
Hello everyone, I have recently discovered the LLVM project and have to say that it looks impressively interesting so far. Kudos to all developers for the good work. However, I am afraid I have a few newbie questions that I have been unable to resolve browsing the documentation. I am evaluating the use of LLVM with respect to a feasibility study for a project. For this project I need to be
2007 Jun 06
4
how hierarchical is HTB?
Hi there! I''ve using HTB for a while and now I an faced with a ''problem''. How hierarchical is HTB? Let''s say I have this 3 layer HTB setup: root class 1: (rate=100, ceil=100) 1: children classes 1:10 (30,100) and 1:20 (70,100) 1:10 children classes 1:100 (10,100) and 1:101 (20,100) 1:20 children classes 1:200 (30,100) and 1:201 (70,100) I managed to have
2007 Apr 18
0
[Bridge] QoS in bridging
Hi all, I have got one query on QoS in bridging in Linux My question is, when we define IP QoS ( using a tc command ) queuing discplines and classses, will these be applicable to bridged frames also ? I mean the packets that take IP path will be sent out according to QoS we defined, but the bridged/ swithced packets will also be sent according to this defined IP QoS classses ? My doubt is that since bridging happens at layer 2, how will it get...
2012 May 09
0
[LLVMdev] instructions requiring specific physical registers for operands
Jim, > The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs: > def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …> > Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required. As
2002 Apr 03
1
Fwd: Re: "weight" parameter in htb?
---------- Forwarded Message ---------- Subject: Re: [LARTC] "weight" parameter in htb? Date: Wed, 3 Apr 2002 10:54:01 +0530 From: Shekhar Joshi <shekhar@disha.co.in> To: lartc@mailman.ds9a.nl On Tuesday 02 April 2002 07:32 pm, you wrote: > On Tue, Apr 02, 2002 at 03:34:08PM +0200, Martin Devera wrote: > > > E.g. you might have a customer agency which needs say 256
2005 Jan 20
5
glm and percentage data with many zero values
Dear all, I am interested in correctly testing effects of continuous environmental variables and ordered factors on bacterial abundance. Bacterial abundance is derived from counts and expressed as percentage. My problem is that the abundance data contain many zero values: Bacteria <-
2012 May 09
2
[LLVMdev] instructions requiring specific physical registers for operands
Hi, I have som instructions that require the operand to be placed in exactly one physical register, and thus I have introduced a Just_a0 register class. I have found that the register allocators / coalescer do not seem to care about this. In many cases they "run out of registers during register allocation". I have managed to avoid some problems, by inserting target move instructions in
2012 May 09
0
[LLVMdev] instructions requiring specific physical registers for operands
Hello Jonas, > I wonder, what would be the best solution for instructions that require > operands in a particular register, and even gives the result in a particular > register? You need to custom select such instruction. See e.g. div / idiv on x86 as an example. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University
2006 Nov 13
0
i have a question with queuing discipline.
i have a question with queuing discipline " if i create many classs with sfq and cbq and ... i would like to know about qos . which queuing discipline will be chosen first. ( not use priority ) (queuing discipline) sfq---------> packet incoming packet outgoing cbq--------> Thank you .
2010 Nov 02
0
tagged not working ?
Hello For some reason I do not seems to be able to get ''tag'' working... env : EC2 Ubuntu, puppet version 2.6.1 (client and puppetmaster) example of my nodes.pp file class puppet_tagged { if tagged("fly-puppet") { file { "/tmp/fly_puppet_server": ensure => "present", mode
2006 Sep 26
0
newbie: Example of using prototype window class
HI guys, I really want to use some of the cool protoype window libs I have seen, im a real dope when it comes to javascript and the such, can someone give me some code hints on how to use a prototype skin classs as my default browser skin for the app I am working on? Also how to open a prototype window from within a ruby app? Is the prototype window lib included with RoR out of the box? thx in
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
..., FSR1]> { let SubRegClassList = [FSR8, FSR8]; // HERE. } SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>; SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>; I think the fundamental problem we have there is that we are using SubIdx for both purposes: 1. to enumerate over subregister classses, 2. To enumerate subregs of the same type of a super reg. - Sanjiv. > > > > > > > > Hope I made it clear. Please write back if they aren't. > > > > > > - Sanjiv > > > > > > > > > > > > > > > >> On O...
2012 Sep 27
2
Puppetdashboard :: cannot add class
I have puppet running on WEBrick. Dashboard works. I can see the hosts currently in puppet. In Dashboard I can add hosts and create groups, but cannot add classes. The auto-search returns nothing when I click on a group or server and start typing in the Classes textbox. Is this a common occurrence with Dashboard? I have looked on the web and found no answer. Appreciate any pointers. Thanks.
2004 Aug 25
0
S3 classes in S4 class definitions
One of the changes some packages are noticing from the recent modifications to methods is warnings of "undefined classes" during installation when the package extends S3 classes or uses them as slots UNLESSS they have been declared in a setOldClass() call. The green book "strongly recommends" declaring S3 classs this way (pp 449-451). The warnings on undeclared classes
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...oon. Thanks, Evan > > > SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>; > SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>; > > > I think the fundamental problem we have there is that we are using > SubIdx for both purposes: 1. to enumerate over subregister > classses, 2. > To enumerate subregs of the same type of a super reg. > > > - Sanjiv. > >>> >>> >>> >>> Hope I made it clear. Please write back if they aren't. >>> >>> >>> - Sanjiv >>> >>> >>> >&g...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote: > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: >> You need to specify sub-register == super-register, idx relationship. >> See X86RegisterInfo.td: >> >> def x86_subreg_8bit : PatLeaf<(i32 1)>; >> def x86_subreg_16bit : PatLeaf<(i32 2)>; >> def x86_subreg_32bit : PatLeaf<(i32
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > You need to specify sub-register == super-register, idx relationship. > See X86RegisterInfo.td: > > def x86_subreg_8bit : PatLeaf<(i32 1)>; > def x86_subreg_16bit : PatLeaf<(i32 2)>; > def x86_subreg_32bit : PatLeaf<(i32 3)>; > > def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, >