search for: classllvm_1_1targetinstrinfo

...Instr bundles seem to difficult to use and too late in the code generation (I prefer working at the level of instruction selection). Also, I found little information about pseudo-instructions - there is some API support, namely expandPostRAPseudo() described at http://llvm.org/docs/doxygen/html/classllvm_1_1TargetInstrInfo.html. Also, some documentation at http://llvm.org/devmtg/2014-04/PDFs/Talks/Building%20an%20LLVM%20backend.pdf, slide 55 (and 53, 54). Please let me know if I can customize the post-RA scheduler to avoid scheduling in non-consecutive cycles my two SDNodes created "together" or if...

Hello, While tuning the MIScheduler for my target, I discovered a code that unnecessarily restricts the scheduler. I think this is a bug, but I would appreciate a second opinion. In file ScheduleDAGInstrs.cpp, the function MIsNeedChainEdge determines whether two MachineInstrs are ordered by a memory dependence. It first runs through the standard criteria (Do both instructions access memory?