search for: classllvm_1_1smallvectorimpl

Displaying 4 results from an estimated 4 matches for "classllvm_1_1smallvectorimpl".

2013 Nov 03
0
[LLVMdev] Appropriate DS for implementing worklist
...end" of the vector, so you'll get LIFO behavior if you use them in that way For LIFO you need to either insert at the front and pop from the back or insert at the back and pop from the front. You can insert at the front using the insert member function ( http://llvm.org/docs/doxygen/html/classllvm_1_1SmallVectorImpl.html#af622128e353515efebccad40eae495cb) and passing the begin iterator. > > Regards, > Rekha > > > On Sun, Nov 3, 2013 at 8:31 PM, David Blaikie <dblaikie at gmail.com> wrote: > >> If you don't care about efficiency you can push (or at least insert) at >&gt...
2013 Nov 03
2
[LLVMdev] Appropriate DS for implementing worklist
Thank you David for prompt reply. I tried with SmallVector. I inserted elements with push_back(). But when I retrieve elements using pop_back_val the elements are returned in reverse order of insertion (I mean like LIFO order). I need this to be FIFO order. How to achieve that? Regards, Rekha On Sun, Nov 3, 2013 at 8:31 PM, David Blaikie <dblaikie at gmail.com> wrote: > If you
2010 Sep 07
0
[LLVMdev] MachineMemOperand and dependence information
On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote: > I have two questions regarding MachineMemOperands and dependence information. > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > (before optimization) > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,