Displaying 1 result from an estimated 1 matches for "classllvm_1_1scheduledagmi".
2017 Feb 10
3
Enforcing in post-RA scheduling to keep (two) MachineInstrs together
Hello.
I am using the post-RA (Register Allocation) scheduler to avoid data hazards by
inserting other USEFUL instructions from the program (besides NOPs) and it breaks apart
some sequences of instructions which should remain "glued" together.
More exactly, in my [Target]ISelDAGToDAG.cpp it is possible that I replace for
example a BUILD_VECTOR with a machine SDNode called