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Hi, I'm in the process of migrating from clang5 to clang10. Unfortunately clang10 introduced a negative performance impact. The cause is an increase of PLT entries from this patch (first released in clang7): https://bugs.llvm.org/show_bug.cgi?id=36370 https://reviews.llvm.org/D43383 If I revert that clang patch locally, the additional PLT entries and the...

...98 <_start>: >> 1298: e8 04 00 00 00 callq 12a1 <foo+0x4> >> >> 000000000000129d <foo>: >> 129d: c3 retq >> >> >> The call to foo does not go through the PLT. That's the behavior seen using clang5. But clang10 generates the PLT32 relocation instead, like this: >> >> $ cat b.s >> .globl _start, foo >> _start: >> .byte 0xe8 >> .reloc ., R_X86_64_PLT32, foo - 4 >> .long foo - . >> foo: >> ret >> >> $ as b.s -o b.o >> $ ld.lld-10...

Hello LLVM Community (specifically anyone working with ARM Cortex-M), While trying to compile the Newlib C library I found that Clang10 was generating slightly larger binaries than the libc from the prebuilt gcc-arm-none-eabi toolchain. I looked at a few specific functions (memcpy, strcpy, etc.) and noticed that LLVM does not tend to generate load/store instructions with a register offset (e.g. ldr Rd, [Rn, Rm] form) and instead pr...

...gt; *To:* llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org> > *Subject:* [llvm-dev] [ARM] Should Use Load and Store with Register Offset > > Hello LLVM Community (specifically anyone working with ARM Cortex-M), > > While trying to compile the Newlib C library I found that Clang10 was > generating slightly larger binaries than the libc from the prebuilt > gcc-arm-none-eabi toolchain. I looked at a few specific functions (memcpy, > strcpy, etc.) and noticed that LLVM does not tend to generate load/store > instructions with a register offset (e.g. ldr Rd, [Rn, Rm]...