search for: clamp

...cket in about 150ms. I want to cut this time down to decrease latency while serving files, so I thought I''d try and reduce the packet size for the offending upload streams (my webserver). The trick is that I also want all other tcp connections to have the normal full packet size. Enter MSS-clamping. My pppoe client for linux can do mss clamping on every packet that goes out and come in. Not enough control. There is an option to do mss-clamping in iptables, however this only works in the forward table. I can''t match and control outgoing web connections, just connections getting rou...

Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > The Tegra124 and later Tegra SoCs have a sepatate rail gating register > to enable/disable the clamp. The original function > tegra_powergate_remove_clamping() is not sufficient for the enable > function. So add a new function which is dedicated to the GPU rail > gating. Also don't refer to the powergate ID since the GPU ID makes no > sense here. > > Signed-off-by: Vince Hsu...

...; } + case OP_CVT: { + Storage res; + bld.setPosition(i, true); /* make sure bld is init'ed */ + switch(i->dType) { + case TYPE_U16: + switch (i->sType) { + case TYPE_F32: + if (i->saturate) + res.data.u16 = util_iround(CLAMP(imm0.reg.data.f32, 0, + UINT16_MAX)); + else + res.data.u16 = util_iround(imm0.reg.data.f32); + break; + case TYPE_F64: + if (i->saturate) + res.data.u16 = util_iround(CLAMP(imm0.r...

...this is not the correct forum for my question, can anyone suggest a better person or place to which I should direct it? Thank you, Jonathan Kamens ------- Start of forwarded message ------- From: Jonathan Kamens <jik@kamens.brookline.ma.us> To: lartc@mailman.ds9a.nl Subject: [LARTC] MSS clamping doesn''t work with masquerading through VPN? Date: Fri, 23 May 2003 12:42:10 -0400 My employer uses a Microsoft VPN concentrator. I followed the instructions at pptpclient.sourceforge.net to add support for that concentrator to my Linux machine; after doing so, I was able to successful...

The Tegra124 and later Tegra SoCs have a sepatate rail gating register to enable/disable the clamp. The original function tegra_powergate_remove_clamping() is not sufficient for the enable function. So add a new function which is dedicated to the GPU rail gating. Also don't refer to the powergate ID since the GPU ID makes no sense here. Signed-off-by: Vince Hsu <vinceh at nvidia.com>...

...m Donnerstag, den 25.12.2014, 10:28 +0800 schrieb Vince Hsu: > On 12/24/2014 09:16 PM, Lucas Stach wrote: > > Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >> The Tegra124 and later Tegra SoCs have a sepatate rail gating register > >> to enable/disable the clamp. The original function > >> tegra_powergate_remove_clamping() is not sufficient for the enable > >> function. So add a new function which is dedicated to the GPU rail > >> gating. Also don't refer to the powergate ID since the GPU ID makes no > >> sense here....

...4->(U16/32, S16/32) and (U16/32, S16/32)->F32 No piglit regressions observed on nv50 and nvc0! Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- V2: fix usage of wrong variable V3: enable F64 support V4: - disable F64 support again - handle saturate flag: clamp to min/max if needed .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index b89da43..c97f8f4 100644 --...

On 12/24/2014 09:16 PM, Lucas Stach wrote: > Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: >> The Tegra124 and later Tegra SoCs have a sepatate rail gating register >> to enable/disable the clamp. The original function >> tegra_powergate_remove_clamping() is not sufficient for the enable >> function. So add a new function which is dedicated to the GPU rail >> gating. Also don't refer to the powergate ID since the GPU ID makes no >> sense here. >> >> S...

...den 25.12.2014, 10:28 +0800 schrieb Vince Hsu: >> On 12/24/2014 09:16 PM, Lucas Stach wrote: >>> Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: >>>> The Tegra124 and later Tegra SoCs have a sepatate rail gating register >>>> to enable/disable the clamp. The original function >>>> tegra_powergate_remove_clamping() is not sufficient for the enable >>>> function. So add a new function which is dedicated to the GPU rail >>>> gating. Also don't refer to the powergate ID since the GPU ID makes no >>>>...

...28:08AM +0800, Vince Hsu wrote: > >>On 12/24/2014 09:16 PM, Lucas Stach wrote: > >>>Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >>>>The Tegra124 and later Tegra SoCs have a sepatate rail gating register > >>>>to enable/disable the clamp. The original function > >>>>tegra_powergate_remove_clamping() is not sufficient for the enable > >>>>function. So add a new function which is dedicated to the GPU rail > >>>>gating. Also don't refer to the powergate ID since the GPU ID makes no >...

Hey, My internet is provided via ADSL using PPPoE. When I take a look at ifconfig''s output, I see that eth0 has an MTU of 1500, and ppp0 has an MTU of 1492. I don''t _think_ that rp-pppoe (my pppoe util) is clamping the MSS. I am noticing some latency when there''s a lot of bandwidth in use (but not >90%). What should I clamp, eth0/ppp0? How much? And what with, rp-pppoe, or tc/iproute2/etc ? I guess I don''t really understand clamping MSS, can someone explain it in laymans terms? I...

...mpting to throttle egress traffic to a specific rate using a tbf. As a starting point I used an example from the LARTC howto, which goes: tc qdisc add dev eth1 root tbf rate 220kbit latency 50ms burst 1540 I then attempt a large fetch from another machine via wget (~40 megs) and the rate was clamped down to about 12Kbytes/s. As this seemed too much, I gradually increased the latency up to 200ms which then gave me the expected results (~34Kbytes/s). I then applied this queuing discipline on a machine acting as a gateway/router for a few VLANed subnets. The tbf was applied on interface...

...25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: >> On 12/24/2014 09:16 PM, Lucas Stach wrote: >>> Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: >>>> The Tegra124 and later Tegra SoCs have a sepatate rail gating register >>>> to enable/disable the clamp. The original function >>>> tegra_powergate_remove_clamping() is not sufficient for the enable >>>> function. So add a new function which is dedicated to the GPU rail >>>> gating. Also don't refer to the powergate ID since the GPU ID makes no >>>>...

...ince Hsu wrote: >>>> On 12/24/2014 09:16 PM, Lucas Stach wrote: >>>>> Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: >>>>>> The Tegra124 and later Tegra SoCs have a sepatate rail gating register >>>>>> to enable/disable the clamp. The original function >>>>>> tegra_powergate_remove_clamping() is not sufficient for the enable >>>>>> function. So add a new function which is dedicated to the GPU rail >>>>>> gating. Also don't refer to the powergate ID since the GPU ID m...

...4->(U16/32, S16/32) and (U16/32, S16/32)->F32 No piglit regressions observed on nv50 and nvc0! Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- V2: fix usage of wrong variable V3: enable F64 support V4: - disable F64 support again - handle saturate flag: clamp to min/max if needed V5: clamp before rounding to nearest uint/int .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir...

On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: > On 12/24/2014 09:16 PM, Lucas Stach wrote: > >Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >>The Tegra124 and later Tegra SoCs have a sepatate rail gating register > >>to enable/disable the clamp. The original function > >>tegra_powergate_remove_clamping() is not sufficient for the enable > >>function. So add a new function which is dedicated to the GPU rail > >>gating. Also don't refer to the powergate ID since the GPU ID makes no > >>sense here. &gt...

...> >>>>On 12/24/2014 09:16 PM, Lucas Stach wrote: > >>>>>Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >>>>>>The Tegra124 and later Tegra SoCs have a sepatate rail gating register > >>>>>>to enable/disable the clamp. The original function > >>>>>>tegra_powergate_remove_clamping() is not sufficient for the enable > >>>>>>function. So add a new function which is dedicated to the GPU rail > >>>>>>gating. Also don't refer to the powergate ID since...

...int32_t count, uint64_t offset, > + struct nbdkit_extents *extents) > +{ > + uint32_t n, type; > + void *p; > + > + while (count > 0) { > + p = lookup (sa, offset, false, &n, NULL); > + if (n > count) > + n = count; Why are we clamping the information we return? I'd move this clamp... > + > + if (p == NULL) > + type = NBDKIT_EXTENT_HOLE | NBDKIT_EXTENT_ZERO; > + else > + type = 0; /* allocated data */ > + if (nbdkit_add_extent (extents, offset, n, type) == -1) > + return -1; ....

...t;>On 12/24/2014 09:16 PM, Lucas Stach wrote: > > >>>>>Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > > >>>>>>The Tegra124 and later Tegra SoCs have a sepatate rail gating register > > >>>>>>to enable/disable the clamp. The original function > > >>>>>>tegra_powergate_remove_clamping() is not sufficient for the enable > > >>>>>>function. So add a new function which is dedicated to the GPU rail > > >>>>>>gating. Also don't refer to the powe...

Every hour I get a mail from logcheck with a line like Nov 6 12:08:34 wheat fetchnews[13617]: clamping maxage for comp.os.linux.admin to global expire 50 The strange thing is that syslog is filled with similar lines, but this is the only one I get in the report. It is the last such line in each group: # many similar lines deleted Nov 6 12:08:32 wheat fetchnews[13617]: comp.std.c++: considering...