Displaying 2 results from an estimated 2 matches for "ciinstructions".
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2016 Mar 28
0
RFC: atomic operations on SI+
...sely <jan.vesely at rutgers.edu>
> Date: Tue, 22 Mar 2016 13:54:55 -0400
> Subject: [PATCH 1/1] AMDGPU,SI: Implement atomic compare and swap
>
> ---
> lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 +
> lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 +
> lib/Target/AMDGPU/CIInstructions.td | 3 +-
> lib/Target/AMDGPU/SIISelLowering.cpp | 41 +++++++++++++++
> lib/Target/AMDGPU/SIISelLowering.h | 1 +
> lib/Target/AMDGPU/SIInstrInfo.td | 9 ++++
> lib/Target/AMDGPU/SIInstructions.td | 2 +-
> test/CodeGen/AMDGPU/global_atomics.ll |...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This