search for: chsw

...PDISP have the debug level Also, my interest is linked to the state of GPU graph given after a context switch timeout that looks like: [ 1696.780305] nouveau 0000:01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] [ 1696.780361] nouveau 0000:01:00.0: fifo:000000:00[ gr]: 8006e005: busy 1 faulted 0 chsw 1 save 1 load 1 chid 5*-> chid 6 [ 1696.780422] nouveau 0000:01:00.0: fifo:000000:07[ ce2]: 00050005: busy 0 faulted 0 chsw 0 save 0 load 0 chid 5 -> chid 5 [ 1696.780476] nouveau 0000:01:00.0: fifo:000004:04[ ce0]: 00000000: busy 0 faulted 0 chsw 0 save 0 load 0 chid 0 -> chid 0...

...g level > > Also, my interest is linked to the state of GPU graph given after a context switch timeout that looks like: > [ 1696.780305] nouveau 0000:01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] > [ 1696.780361] nouveau 0000:01:00.0: fifo:000000:00[ gr]: 8006e005: busy 1 faulted 0 chsw 1 save 1 load 1 chid 5*-> chid 6 > [ 1696.780422] nouveau 0000:01:00.0: fifo:000000:07[ ce2]: 00050005: busy 0 faulted 0 chsw 0 save 0 load 0 chid 5 -> chid 5 > [ 1696.780476] nouveau 0000:01:00.0: fifo:000004:04[ ce0]: 00000000: busy 0 faulted 0 chsw 0 save 0 load 0 chid 0 -&gt...

...base.lock, flags); for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) { - u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); + u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); u32 busy = (stat & 0x80000000); u32 next = (stat & 0x07ff0000) >> 16; u32 chsw = (stat & 0x00008000); -- 2.1.4

...w(struct gk104_fifo *fifo) for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) { u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); u32 busy = (stat & 0x80000000); - u32 next = (stat & 0x07ff0000) >> 16; + u32 next = (stat & 0x0fff0000) >> 16; u32 chsw = (stat & 0x00008000); u32 save = (stat & 0x00004000); u32 load = (stat & 0x00002000); - u32 prev = (stat & 0x000007ff); + u32 prev = (stat & 0x00000fff); u32 chid = load ? next : prev; (void)save; -- 2.7.1

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and

...tput (about 50000 lines, I think), starting Mar 28 16:39:00 origin kernel: [41644.858087] nouveau 0000:26:00.0: fifo: FB_FLUSH_TIMEOUT Mar 28 16:40:02 origin kernel: [41707.692180] nouveau 0000:26:00.0: fifo: FB_FLUSH_TIMEOUT Mar 28 16:40:02 origin kernel: [41707.692215] nouveau 0000:26:00.0: fifo: CHSW_ERROR 00000001 Mar 28 16:40:02 origin kernel: [41707.692264] nouveau 0000:26:00.0: fifo: CHSW_ERROR 00000003 Mar 28 16:40:16 origin kernel: [41720.825498] nouveau 0000:26:00.0: fifo: CHSW_ERROR 00000002 Mar 28 16:40:16 origin kernel: [41720.825502] nouveau 0000:26:00.0: fifo: FB_FLUSH_TIMEOUT Mar 2...

...uman-readable mmu fault descriptions e9fb980 drm/nve0/fifo: document more intr status bits 9f8459c drm/nve0/fifo: populate PBDMA status bitfield with more definitions 39b0554 drm/nve0/fifo: s/subfifo/PBDMA/ f82c44a drm/nve0/fifo: s/playlist/runlist/ f76dd80 drm/nvf0/gr: enable acceleration with our chsw ucode aa97cd3 drm/nv108/gr: enable acceleration with our chsw ucode 5d91e19 drm/nvc0-/gr: handle fwmthd interrupts in ucode e1b22bc drm/nvc0-/gr: fiddle some magic around strand init 96616b4 drm/nv108/gr: initial support (need external fuc) daa9ab5 drm/nv108/ce: enable copy engines a763951 drm/nv10...

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations