search for: chih

Thanks Quentin. I'm trying to examine from the operands of the return instruction, and then to get the last assignment of those. I thought use_iterator/reg_iterator may suit better than just loop through the machine basicblock in the reverse order. Cheng-Chih On Thu, Sep 25, 2014 at 1:51 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Cheng-Chih, > > On Sep 25, 2014, at 9:14 AM, Yang, Cheng-Chih <Cheng-Chih.Yang at amd.com> > wrote: > > Hi folks, > > I would like to find out the machine instructions that u...

...king through "Writing an LLVM pass" documentation, it's not clear to me if this is possible. I've also tried putting the pass in different orders (addPreISel, addIRPasses, and etc.). Am I missing something or this is just not possible to do? Any help is appreciated. Thanks, Cheng-Chih -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140930/78e83ad1/attachment.html>

...r as the machine function? Maybe from the order that DAG is constructed? 2) Is there a way to go backward with these two iterators? For example, from use_end() to use_begin() with some decrement operator? I was wondering if 1) and 2) are true or just there's something I missed. Thanks! Cheng-Chih -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140925/ded4eed5/attachment.html>

...n value which is defined from outside of the function. I could, at the ISelLowering stage when seeing an ADD, replace the “%0” with a i32 constant 0, but I don’t feel like this is the right approach. Should I try to look into SUBREG_TO_REG/INSERT_REG here? Or any other thoughts? Thanks, - Cheng-Chih

Hi folks, I'm running into this weird issue where the register spills appear to be missing for an "if" block for some reason. For example, the original if/else blocks: --- if reg0 // storeRegToStackSlot for reg1 // do something - missing a load for reg1? else // storeRegToStackSlot for reg1 // do something // loadRegFromStackSlot for reg1 end ---- I tried looking in the LLVM

Hi, I heard that Theora will be used on OLPC. Is anyone working on optimization for OLPC? Regards, Chih-Chung Chang

Hello Everyone, I am new with XCP. I''ve setup several hosts with* XCP 1.0* and manage it through XenCenter and command console. Each host has two NICs, one (xenbr0) connected to a physical switch for Internet (said sw1), the other (xenbr3) connected to a physical switch for internal network (said sw2). I am trying to setup VMs and VLANs on xenbr3. I created a virtual bridge by

...f I read the spec correctly) * comment out unused idct_short__c, remove unused LoopFilterLimitValuesV2 An --enable-mmx option is added to configure (you need to run autogen.sh to enable it after patch). Compile time switch is used instead of a runtime one because it seems easier to me :) Regards, Chih-Chung Chang -------------- next part -------------- A non-text attachment was scrubbed... Name: theora.patch.20070326.gz Type: application/x-gzip Size: 14900 bytes Desc: not available Url : http://lists.xiph.org/pipermail/theora-dev/attachments/20070326/5fc3c925/theora.patch.20070326.bin

Hi, I''m new to this mailing list, so first off, a big THANK YOU for the script.aculo.us and prototype.js libraries. I''m trying to integrate script.aculo.us into an existing pretty large Javascript codebase (see http://openrecord.org). I''m running into a problem with prototype.js and the existing codebase''s use of for/in loops over an Array.

...w places in type legalizing pass and some other optimizations related to f128 or i128 values. A few changes in the softening of floating point types to keep some f128 typed IR and convert some f128 opcode to library function calls. Has anyone tried this approach or have other solution? Thanks -- Chih-Hung -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150713/b39948d1/attachment.html>

Hi Folks, We''re moving from a single lighttpd-hosted Rails box to a Apache/ mongrel cluster. In lighttpd, mod_compress had a very nice feature: if there''s a static file, it would compress it in a user-specified compress folder. If the file hasn''t changed, it would just serve out the compress file; if the file has changed, it would recompress it and serve it out.

Dear all: I have six vector from six DIF detection results. as below: > difMH[[100]]$DIFitems [1] 1 9 19 21 22 24 25 27 29 30 34 38 40 > difMH[[90]]$DIFitems [1] 1 2 9 14 18 19 21 22 25 28 30 34 38 39 > difMH[[80]]$DIFitems [1] 1 8 9 19 21 22 24 25 26 28 30 34 38 > difMH[[70]]$DIFitems [1] 1 8 9 10 16 18 21 22 25 28 30 32 34 38 39 > difMH[[60]]$DIFitems [1] 1 9 19

Hi, I am using axis() to plot axis 1 and axis 2. but now when I used axis(side=1,....) and axis(side=2,.....), there's a big margin between these two axis. does anybody have any idea about how to shrink the margin between these two axis. basically, I want to move axis 1 left so that when I plot axis 3, the margin between axis 1 and 2 and margin between axis 1 and 4 are the same. like this

...ING[16384]: loader.c:408 load_modules: Loading module app_dtmftotext.so failed! Ouch ... error while writing audio data: : Broken pipe [root@zapata root]# Warning, flexible rate not heavily tested! Please help! -- Manuel Marin Garcia TRANSTELCO S.A. DE C.V. Campos Eliseos 9050 B4 – Cd. Juárez, Chih. 32452 - México Oficina: +52 656 692 11 09 – Fax: +52 656 692 1112 - Celular: 915 727 6141 http://www.transtelco.com.mx

Chih-Wei Huang wrote: > Hi, > I just install tinc 1.0pre3 by rpm. > When I tried to start tincd by > /etc/rc.d/init.d/tinc start > It complained > **tinc: file with list of VPNs to start (/etc/tinc/nets.boot) not found! > However, I don't know what /etc/tinc/nets.boot is. > I...

...switching to using 'llvm-lld' instead of Gnu 'ld' in a future revision of our out-of-tree target, and I am wondering is there a getting started guide for how to go about extending 'llvm-lld' to support an additional target. I don't believe there is, but the patches from Chih-Mao Chen for RISC-V support seemed well structured to me, so may be useful to learn from: * https://reviews.llvm.org/D39322 * https://reviews.llvm.org/D39323 * https://reviews.llvm.org/D39324 As a side note: if any LLD devs have time to review these patches, it would be hugely appreciated. Best,...

...coroutines? - Jonathan and other OpenMP folks: it's no longer behind a flag; would be great to get some notes on this. - Artem: there's been a bunch of CUDA patches. Anything that should be mentioned in the release notes? - Jordan & Anna: any new checkers that should be mentioned? - Chih-Hung: should the notes mention the emutls-style TLS model? - Lang: you did a lot of work on the Kalidoscope tutorial. Maybe we should mention that? .. tell me what I missed :-) Thanks, Hans [1]. http://llvm.org/pre-releases/3.8.0/#rc2.

...y working on adding support for RISC-V in lld, and RISC-V heavily relies on linker relaxation to remove extraneous code and to handle alignment. Since linker relaxation may be of interest to other targets as well, I'm wondering what would be a good way to modify lld to support that. Thanks. -- Chih-Mao Chen (PkmX) Software R&D, Andes Technology

Full_Name: Julien Gagneur Version: 2.2.1 OS: Linux (Suse 9.3) Submission from: (NULL) (194.94.44.4) Using the SparseM library (SparseM_0.66) and the e1071 library (e1071_1.5-12) I fail using svm method with a sparse matrix. Here is a sample example. I experienced the same problem under Windows. > library(SparseM) [1] "SparseM library loaded" > library("e1071")

Just a Question. I would like to know if TDMoE follows specifiaciones of TDMoIP RAD protocol that says that there is a compression of 16/1 when you do TDMoIP. Manuel Marin Garcia TRANSTELCO S.A. DE C.V. Campos Eliseos 9050 B4 – Cd. Juárez, Chih. 32452 - México Oficina: +52 656 692 11 09 – Fax: +52 656 692 1112 - Celular: 915 727 6141 http://www.transtelco.com.mx