search for: chid

...level Also, my interest is linked to the state of GPU graph given after a context switch timeout that looks like: [ 1696.780305] nouveau 0000:01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] [ 1696.780361] nouveau 0000:01:00.0: fifo:000000:00[ gr]: 8006e005: busy 1 faulted 0 chsw 1 save 1 load 1 chid 5*-> chid 6 [ 1696.780422] nouveau 0000:01:00.0: fifo:000000:07[ ce2]: 00050005: busy 0 faulted 0 chsw 0 save 0 load 0 chid 5 -> chid 5 [ 1696.780476] nouveau 0000:01:00.0: fifo:000004:04[ ce0]: 00000000: busy 0 faulted 0 chsw 0 save 0 load 0 chid 0 -> chid 0 [ 1696.780529] nouv...

...o, my interest is linked to the state of GPU graph given after a context switch timeout that looks like: > [ 1696.780305] nouveau 0000:01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] > [ 1696.780361] nouveau 0000:01:00.0: fifo:000000:00[ gr]: 8006e005: busy 1 faulted 0 chsw 1 save 1 load 1 chid 5*-> chid 6 > [ 1696.780422] nouveau 0000:01:00.0: fifo:000000:07[ ce2]: 00050005: busy 0 faulted 0 chsw 0 save 0 load 0 chid 5 -> chid 5 > [ 1696.780476] nouveau 0000:01:00.0: fifo:000004:04[ ce0]: 00000000: busy 0 faulted 0 chsw 0 save 0 load 0 chid 0 -> chid 0 > [ 1696....

...4,7 @@ #include <core/os.h> #include <core/class.h> +#include <core/client.h> #include <core/engctx.h> #include <core/namedb.h> #include <core/handle.h> @@ -398,10 +399,29 @@ out: return handled; } +static struct nouveau_client * +nv04_fifo_client_for_chid(struct nv04_fifo_priv *priv, u32 chid) +{ + struct nouveau_fifo_chan *chan; + struct nouveau_client *client = NULL; + unsigned long flags; + + spin_lock_irqsave(&priv->base.lock, flags); + if (chid >= priv->base.min && + chid <= priv->base.max) { + chan = (void *)priv-...

...o/nv04.c index 2fe14da3..76944c4 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c @@ -398,6 +398,92 @@ out: return handled; } +static void +nv04_fifo_cache_error(struct nouveau_device *device, + struct nv04_fifo_priv *priv, u32 chid, u32 get) +{ + u32 mthd, data; + int ptr; + + /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my + * G80 chips, but CACHE1 isn't big enough for this much data.. Tests + * show that it wraps around to the start at GET=0x800.. No clue as to + * why.. + */ + ptr = (get & 0...

...I have had my mouse pointer disappear soon after logging in, and I have observed the system freezing temporarily when clicking on objects and when typing text. I have also found records of push buffer errors in dmesg output: [ 6625.450394] nouveau 0000:01:00.0: disp: ERROR 1 [PUSHBUFFER_ERR] 02 [] chid 0 mthd 0000 data 00000400 I tried setting CONFIG_NOUVEAU_DEBUG=5 (tracing) to try and collect further debug info, but nothing caught the eye. The error message in question comes from nv50_disp_intr_error in drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c:613,645. And nv50_disp_intr_error is calle...

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations

...u/nvkm/engine/disp/changf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c @@ -52,7 +52,7 @@ void gf119_disp_chan_intr(struct nv50_disp_chan *chan, bool en) { struct nvkm_device *device = chan->disp->base.engine.subdev.device; - const u64 mask = 0x00000001 << chan->chid.user; + const u64 mask = 0x00000001ULL << chan->chid.user; if (!en) { nvkm_mask(device, 0x610090, mask, 0x00000000); nvkm_mask(device, 0x6100a0, mask, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c...

https://bugs.freedesktop.org/show_bug.cgi?id=73924 Priority: medium Bug ID: 73924 Assignee: nouveau at lists.freedesktop.org Summary: E[ PDISP][0000:01:00.0] chid 0 mthd 0x0080 data 0x00000000 0x00055080 QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified OS: All Reporter: mikhail.v.gavrilov at gmail.com Hardware: Other Status: NEW...

https://bugs.freedesktop.org/show_bug.cgi?id=96968 Bug ID: 96968 Summary: [NVC0] disp: ERROR 7 [INVALID_HANDLE] 00 [] chid 0 mthd 0088 data f000000 Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assigne...

https://bugs.freedesktop.org/show_bug.cgi?id=99858 Bug ID: 99858 Summary: disp: ERROR 4 [INVALID_VALUE] 84 [] chid 0 mthd 0828 data 000099bb Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assign...

...32 next = (stat & 0x07ff0000) >> 16; + u32 next = (stat & 0x0fff0000) >> 16; u32 chsw = (stat & 0x00008000); u32 save = (stat & 0x00004000); u32 load = (stat & 0x00002000); - u32 prev = (stat & 0x000007ff); + u32 prev = (stat & 0x00000fff); u32 chid = load ? next : prev; (void)save; -- 2.7.1

This series fixes some intermittent issues with bringing up the dedicated GM107 GPU that I've been observing on my ThinkPad P50. More details within. Lyude Paul (2): drm/nouveau: Fix GM107 disp core chan init on ThinkPad P50 drm/nouveau: Fix GM107 disp dmac chan init on ThinkPad P50 .../drm/nouveau/nvkm/engine/disp/coregf119.c | 21 +++++++++++++++++--

...t; sufficiently low risk. > > TBH, I was hoping someone would see the odd "Disp" output and pop in > with an "I know what that is." /-: OK, I'm pretty sure this is from gf119_disp_intr_error: drm/nouveau/nvkm/engine/disp/gf119.c: nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); However what's odd is that preceding this line, there should have been a nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n", chid, (mthd & 0x0000ffc), data, mthd, unkn); which isn't displayed. Furthermore, your logs appe...

...(0 3 4) [ 1.604858] nouveau 0000:01:00.0: disp: outp 04:0006:0f81: aux power -> always [ 1.605354] nouveau 0000:01:00.0: disp: outp 04:0006:0f81: aux power -> demand [ 1.605815] nouveau 0000:01:00.0: disp: outp 05:0002:0f81: no heads (0 3 2) [ 1.607289] nouveau 0000:01:00.0: disp: chid 0 mthd 0000 data 00000400 00001000 00000002 [ 1.608818] nouveau 0000:01:00.0: disp: chid 1 mthd 0000 data 00000400 00001000 00000002 [ 1.609500] nouveau 0000:01:00.0: disp: chid 2 mthd 0000 data 00000400 00001000 00000002 Which of course, later causes other parts of the card to start timing...

...>] stub_clone+0x69/0x90 [ 25.163234] [<ffffffff816ffe29>] ? system_call_fastpath+0x16/0x1b [ 25.163237] ---[ end trace da86bd3f343ad454 ]--- [ 25.163241] ------------[ cut here ]------------ and when using it thousands of lines with [ 342.347721] nouveau E[ PDISP][0000:01:00.0] chid 0 mthd 0x0080 data 0x00000000 0x10005080 0x0000400d [ 342.360259] nouveau E[ PDISP][0000:01:00.0] chid 0 mthd 0x0080 data 0x00000000 0x10005080 0x0000400d [ 342.373450] nouveau E[ PDISP][0000:01:00.0] chid 0 mthd 0x0080 data 0x00000000 0x10005080 0x0000400d [ 342.386710] nouveau E[ PDISP][...

...del(struct nouveau_channel *chan) struct drm_device *dev = chan->drm->dev; struct nv84_fence_priv *priv = chan->drm->fence; struct nv84_fence_chan *fctx = chan->fence; + struct nouveau_fifo_chan *fifo = (void *)chan->object; int i; + nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, fctx->base.sequence); + for (i = 0; i < dev->mode_config.num_crtc; i++) { struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); @@ -168,7 +171,7 @@ nv84_fence_context_new(struct nouveau_channel *chan) ret = nouveau_bo...

..._software.c +++ b/drivers/gpu/drm/nouveau/nvc0_software.c @@ -38,6 +38,7 @@ struct nvc0_software_priv { struct nvc0_software_chan { struct nouveau_software_chan base; struct nouveau_vma dispc_vma[4]; + u32 class[8]; }; u64 @@ -67,6 +68,40 @@ nvc0_software_method(struct drm_device *dev, u32 chid, u32 class, u32 mthd, u32 return handled; } +bool +nve0_software_method(struct drm_device *dev, u32 chid, u32 subc, u32 mthd, u32 data) +{ + struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO); + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nvc0_software...

...index 7b372a68aa4e..4138db4d8291 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -120,6 +120,7 @@ nv84_fence_context_del(struct nouveau_channel *chan) nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); } + nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); nouveau_bo_vma_del(priv->bo, &fctx->vma); nouveau_fence_context_del(&fctx->base); @@ -159,8 +160,6 @@ nv84_fence_context_new(struct nouveau_channel *chan) ret = nouveau_bo_vma_add(b...

https://bugs.freedesktop.org/show_bug.cgi?id=87436 Bug ID: 87436 Summary: INVALID_STATE [UNK05] chid 0 mthd 0x0080 data 0x00000000 Product: xorg Version: 7.7 (2012.06) Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau...

...ct nouveau_channel **pevo) nouveau_bo_ref(NULL, &evo->push.buffer); if (evo->object) - iounmap(evo->object->oclass->ofuncs); + iounmap(((struct evo_object *)evo->object)->iomem); kfree(evo); } @@ -112,6 +117,7 @@ nv50_evo_channel_new(struct drm_device *dev, int chid, struct nouveau_drm *drm = nouveau_drm(dev); struct nv50_display *disp = nv50_display(dev); struct nouveau_channel *evo; + struct evo_object *evo_object; int ret; evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL); @@ -142,7 +148,8 @@ nv50_evo_channel_new(struct drm_device *dev,...