Displaying 1 result from an estimated 1 matches for "checkregoperand".
2018 May 10
2
[RFC] MC support for variant scheduling classes.
...LR}]>;
```
This tablegen code snippet has been taken from
AArch64/AArch64SchedExynosM3.td
Predicate `M3BranchLinkFastPred` can be rewritten using an MCSchedPredicate
definition as follows:
```
def M3BranchLinkFastPred : MCSchedPredicate<
CheckAllOf<[
CheckOpcode<[BLR]>,
CheckRegOperand<0>,
CheckNot<CheckRegOperandValue<0, LR>>]>
>;
```
The MCSchedPredicate uses a `CheckAllOf`, which is a "composition of
predicates", and returns true only if every predicate in the composition
returns true. Note that `CheckAllOf`, `CheckOpcode`, `CheckRegOpe...