Displaying 2 results from an estimated 2 matches for "cgep1".
Did you mean:
gep1
2019 Jun 30
6
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...nstead of an “add” instruction like LLVM 7.0.
This is the while.body excerpt after "CodeGen Prepare” in LLVM 9.0
while.body: ; preds = %entry.old, %while.body
%lsr.iv = phi i32 [ %math, %while.body ], [ -100, %entry.old ]
%res.addr.04 = phi i32* [ %cgep1, %while.body ], [ %res, %entry.old ]
%a.addr.03 = phi i32* [ %cgep, %while.body ], [ %a, %entry.old ]
%6 = load i32, i32* %a.addr.03, align 4, !tbaa !2
store i32 %6, i32* %res.addr.04, align 4, !tbaa !2
%7 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lsr.iv, i32 1)
%math = extract...
2019 Jul 01
0
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...instead of an “add” instruction like LLVM 7.0.
This is the while.body excerpt after "CodeGen Prepare” in LLVM 9.0
while.body: ; preds = %entry.old, %while.body
%lsr.iv = phi i32 [ %math, %while.body ], [ -100, %entry.old ]
%res.addr.04 = phi i32* [ %cgep1, %while.body ], [ %res, %entry.old ]
%a.addr.03 = phi i32* [ %cgep, %while.body ], [ %a, %entry.old ]
%6 = load i32, i32* %a.addr.03, align 4, !tbaa !2
store i32 %6, i32* %res.addr.04, align 4, !tbaa !2
%7 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lsr.iv, i32 1)
%math = extract...