Displaying 7 results from an estimated 7 matches for "cgen".
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2009 Apr 13
0
[LLVMdev] Porting LLVM backend is no fun yet
.../articles/article.aspx?p=1215438): "In
> contrast, every time I look at the GCC code, it takes two people to
> prevent me from clawing my eyeballs out."
>
> I'm sorry to report that so-far I have had the opposite experience.
> Some years ago, I ported binutils (via CGEN) and GCC to an embedded
> RISC CPU and found it the process straightforward and pleasant.
> CGEN was especially handy for describing a sometimes quirky RISC
> instruction set and offered great flexibility for factoring-out
> commonalities. By contrast, I have found TableGen to...
2009 Apr 12
9
[LLVMdev] Porting LLVM backend is no fun yet
...e
http://www.informit.com/articles/article.aspx?p=1215438): "In contrast,
every time I look at the GCC code, it takes two people to
prevent me from clawing my eyeballs out."
I'm sorry to report that so-far I have had the opposite experience.
Some years ago, I ported binutils (via CGEN) and GCC to an embedded RISC
CPU and found it the process straightforward and pleasant. CGEN was
especially handy for describing a sometimes quirky RISC instruction set
and offered great flexibility for factoring-out commonalities. By
contrast, I have found TableGen to be much more rigid and...
2012 Aug 01
17
[PATCH] add crtime to the snapshot list
...it (send-v2)
respectively.
Further this patch has the dependency on the following patches
Liu Bo:
[PATCH 2/3 RESEND] Btrfs-progs: show generation in command btrfs subvol list
[PATCH 3/3] Btrfs-progs: list snapshots by generation
Eg output:
#btrfs su list -s 1 /btrfs
ID 258 gen 39 cgen 6 top level 5 crtime 2012-07-27 17:43:55 path ss1
ID 260 gen 8 cgen 8 top level 5 crtime 2012-07-27 17:47:51 path ss2
ID 263 gen 16 cgen 16 top level 5 crtime 2012-07-29 00:50:19 path ss3
ID 264 gen 25 cgen 25 top level 5 crtime 2012-07-30 09:56:50 path sv1/.snap
Anand Jain (1):
Btrfs-p...
2013 Apr 11
0
[PATCH] Btrfs-progs: enhance 'btrfs subvolume list'
...es shall be
printed. This is necessary because this commit also adds all the so
far missing items from the root_item like the received UUID, all
generation values and all time values.
The parameters to the "--fields" option is a list of items to print:
--fields=gen,dirid,uuid,puuid,ruuid,cgen,ogen,sgen,rgen,ctime,otime,
stime,rtime,path,rootid,parent,topid,all
Signed-off-by: Stefan Behrens <sbehrens@giantdisaster.de>
---
btrfs-list.c | 418 ++++++++++++++++++++++++++++++++++++-------------------
btrfs-list.h | 40 +++++-
cmds-subvolume.c | 57 +++-----
man/btrfs.8.in...
2009 Apr 13
0
[LLVMdev] Porting LLVM backend is no fun yet
.../articles/article.aspx?p=1215438): "In
> contrast, every time I look at the GCC code, it takes two people to
> prevent me from clawing my eyeballs out."
>
> I'm sorry to report that so-far I have had the opposite experience.
> Some years ago, I ported binutils (via CGEN) and GCC to an embedded
> RISC CPU and found it the process straightforward and pleasant.
> CGEN was especially handy for describing a sometimes quirky RISC
> instruction set and offered great flexibility for factoring-out
> commonalities. By contrast, I have found TableGen to...
2009 Apr 13
0
[LLVMdev] Porting LLVM backend is no fun yet
.../articles/article.aspx?p=1215438): "In
> contrast, every time I look at the GCC code, it takes two people to
> prevent me from clawing my eyeballs out."
>
> I'm sorry to report that so-far I have had the opposite experience.
> Some years ago, I ported binutils (via CGEN) and GCC to an embedded
> RISC CPU and found it the process straightforward and pleasant.
> CGEN was especially handy for describing a sometimes quirky RISC
> instruction set and offered great flexibility for factoring-out
> commonalities. By contrast, I have found TableGen to...
2011 Mar 15
2
[LLVMdev] Noob Backend Orientation
...sed on SID). I want to make it easier for software engineers to produce code for this architecture so I'm moving onto the next phase by attempting a C compiler, so here I am.
First, I would rather not maintain two different descriptions of the assembly/ISA specification, one in binutils/SID (CGEN) and another in LLVM. I have found some posts about the LLVM MC project, that it can essentially produce an inline or standalone assembler, but is the MC project ready for prime-time? Should I invest my time going this route? It's hard to get a sense of what direction the project is moving i...