search for: cfgs

...Module&) + 33 13 opt 0x00000000007a14a6 main + 3438 14 libc.so.6 0x00000037ee61e074 __libc_start_main + 244 15 opt 0x00000000007929a9 Stack dump: 0. Program arguments: opt -load /u1/suri/llvm-local/build/x86-64/Debug/llvm/Debug/lib/dfl.so -dfl /u1/suri/suri/testing/cfgs/test99foo.c.bc 1. Running pass 'Function Pass Manager' on module '/u1/suri/suri/testing/cfgs/test99foo.c.bc'. 2. Running pass 'emit cfg in dfl format' on function '@main' Surinder >

...st2/target2:0:0/2:0:0:0 sg3-utils are also installed on the system but sg_scan -i returns nothing Output of /proc/bus/usb/devices T: Bus=04 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=12 MxCh= 2 B: Alloc= 0/900 us ( 0%), #Int= 0, #Iso= 0 D: Ver= 1.10 Cls=09(hub ) Sub=00 Prot=00 MxPS= 8 #Cfgs= 1 P: Vendor=0000 ProdID=0000 Rev= 2.06 S: Manufacturer=Linux 2.6.9-5.0.3.EL uhci_hcd S: Product=UHCI Host Controller S: SerialNumber=0000:00:1d.2 C:* #Ifs= 1 Cfg#= 1 Atr=c0 MxPwr= 0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub E: Ad=81(I) Atr=03(Int.) MxPS= 2 Ivl=25...

...running an up to date Centos 4.2 albeit with the 2.6.9-27 SMP kernel. Here are the devices on the USB: # cat /proc/bus/usb/devices T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=12 MxCh= 4 B: Alloc= 27/900 us ( 3%), #Int= 2, #Iso= 0 D: Ver= 1.10 Cls=09(hub ) Sub=00 Prot=00 MxPS= 8 #Cfgs= 1 P: Vendor=0000 ProdID=0000 Rev= 2.06 S: Manufacturer=Linux 2.6.9-27.ELsmp ohci_hcd S: Product=OHCI Host Controller S: SerialNumber=0000:02:00.0 C:* #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr= 0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub E: Ad=81(I) Atr=03(Int.) MxPS= 2 Ivl=25...

Hi LLVMers, I am fairly new to the LLVM pass framework. My goal is to extend the CFGPrinter analysis pass to label the edges of the graph with their edge-counts from profile data. I can generate the CFGs using 'analyze', but I am having trouble loading the profile data. I added the line AU.addRequired<ProfileInfo>(); to the getAnalysisUsage. It is returning zero for all the edge counts. In llvm/Analysis/ProfileInfo.h, I noticed a prototype: Pass *createProfileLoaderPass(const std:...

...node is in a cycle or not must be a relatively > common query. E.g., we used this on DS graphs to decide if DS node > represented multiple objects or a single object. It's the basic query > to decide if a function is part of a recursive computation (a cycle in > the call graph). CFGs happen to have special code for natural loops > but you could use this query to handle irreducible loops as well. These typically don't use the scciterator though. -Chris

I am trying to implement node splitting to transform irreducible CFGS to reducible ones. This means making copies of some basic blocks, which in turn means making copies of individual instructions. I can use the "clone" function to make an exact copy, but then I need to change some operands. For example, when I copy %1 = ... %2 = add %1, 5 I get...

..., i assumed that it is easier for the "receiving" OpenCL compiler to recover the original CFG with the landing block approach. It seems much harder to identify duplicate blocks than to trace a successor through the landing block. The idea behind axtor was to make functions with arbitrary CFGs work on GPUs (usual exceptions apply: no fnc/block ptrs), such that a reliable OpenCL backend becomes feasible. On Mon, 2012-03-05 at 21:07 +0000, Villmow, Micah wrote: > Simon, > Have you looked at the control flow structizer that we have in the Open Source AMDIL backend? > > >...

...ive question. I think that MLIR is closer to > LLVM-IR for how it is processed. Both have a sequence of passes running > over a single source of truth. Both allow walking the entire structure from > every instruction/operation/block. Analyses are on function or module > level. Both have CFGs (I think for a certain kind of transformations it is > an advantage that control flow is handled implicitly). > > > Right, but a frequent way that MLIR is used is without its CFG: most > machine learning kernels use nests of loops and ifs, not CFGs. CFGs are > exposed when those...

...s definitely subjective question. I think that MLIR is closer to LLVM-IR for how it is processed. Both have a sequence of passes running over a single source of truth. Both allow walking the entire structure from every instruction/operation/block. Analyses are on function or module level. Both have CFGs (I think for a certain kind of transformations it is an advantage that control flow is handled implicitly). For > instance, it also does not feature cheap copies. > > > I’m not sure what this means. > > The possibility to make local changes speculatively without copying the entir...

...ew device (0000/0000) found 0 (-1) No USB/HID UPS found stuart@tyro:~+ cat /proc/bus/usb/devices=20 T: Bus=3D02 Lev=3D00 Prnt=3D00 Port=3D00 Cnt=3D00 Dev#=3D 1 Spd=3D12 MxC= h=3D 2 B: Alloc=3D 0/900 us ( 0%), #Int=3D 0, #Iso=3D 0 D: Ver=3D 1.10 Cls=3D09(hub ) Sub=3D00 Prot=3D00 MxPS=3D 8 #Cfgs=3D 1 P: Vendor=3D0000 ProdID=3D0000 Rev=3D 2.06 S: Manufacturer=3DLinux 2.6.10 uhci_hcd S: Product=3DIntel Corp. 82801BA/BAM USB (Hub #2) S: SerialNumber=3D0000:00:1f.4 C:* #Ifs=3D 1 Cfg#=3D 1 Atr=3Dc0 MxPwr=3D 0mA I: If#=3D 0 Alt=3D 0 #EPs=3D 1 Cls=3D09(hub ) Sub=3D00 Prot=3D00 Driver= =3D...

Hi, this is a follow-up on my email from august (http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-August/042737.html). i have, finally, released my OpenCL backend and control-flow restructuring framework for LLVM (AST-Extractor, or short axtor). The framework restructures function CFGs such that they can be expressed entirely without GOTOs or switch/loop-trickery. Hence, making it possible to emit source-code for strictly control-flow structured languages (OpenCL, GLSL). The code includes a drop-in OpenCL driver that allows source-to-source OpenCL code transformations on existing...

...1.1 root hub Bus 002 Device 002: ID 051d:0003 American Power Conversion UPS Bus 002 Device 003: ID 0e0f:0002 VMware, Inc. Virtual USB Hub joavma01:/usr/local/ups/bin # usb-devices T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 6 D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=1d6b ProdID=0002 Rev=02.06 S: Manufacturer=Linux 2.6.32.54-0.3-default ehci_hcd S: Product=EHCI Host Controller S: SerialNumber=0000:02:03.0 C: #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr=0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub T: Bus=02 Lev=00 Prnt=00 Port=00 Cn...

...sier for the "receiving" OpenCL > compiler to recover the original CFG with the landing block approach. It > seems much harder to identify duplicate blocks than to trace a successor > through the landing block. > > The idea behind axtor was to make functions with arbitrary CFGs work on > GPUs (usual exceptions apply: no fnc/block ptrs), such that a reliable > OpenCL backend becomes feasible. > > On Mon, 2012-03-05 at 21:07 +0000, Villmow, Micah wrote: > > Simon, > > Have you looked at the control flow structizer that we have in the > Open Sour...

...e 002: ID 0e0f:0003 VMware, Inc. Virtual Mouse Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub ============================================= usb-devices returns this: T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 6 D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=1d6b ProdID=0002 Rev=03.10 S: Manufacturer=Linux 3.10.0-693.el7.x86_64 ehci_hcd S: Product=EHCI Host Controller S: SerialNumber=0000:02:01.0 C: #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr=0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub T: Bus=02 Lev=00 Prnt=00 Port=00 Cn...

...e 002: ID 0e0f:0003 VMware, Inc. Virtual Mouse Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub ============================================= usb-devices returns this: T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 6 D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=1d6b ProdID=0002 Rev=03.10 S: Manufacturer=Linux 3.10.0-693.el7.x86_64 ehci_hcd S: Product=EHCI Host Controller S: SerialNumber=0000:02:01.0 C: #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr=0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub T: Bus=02 Lev=00 Prnt=00 Port=00 Cn...

...e 002: ID 0e0f:0003 VMware, Inc. Virtual Mouse Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub ============================================= usb-devices returns this: T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 6 D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=1d6b ProdID=0002 Rev=03.10 S: Manufacturer=Linux 3.10.0-693.el7.x86_64 ehci_hcd S: Product=EHCI Host Controller S: SerialNumber=0000:02:01.0 C: #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr=0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub T: Bus=02 Lev=00 Prnt=00 Port=00 Cn...

...IP based gateway to the PSTN from Asterisk. I have been unable to identify through the docs how specifically this should be configured in Asterisk and have not been able to get things working through trial and error. I am sure I am missing something fairly obvious here but any guidance (or example cfgs) would be much appreciated. Rgds, Adam ********* DISCLAIMER ********* This message and any attachment are confidential and may be privileged or otherwise protected from disclosure and may include proprietary information. If you are not the intended recipient, please telephone or email the send...

...ver fully explored, but in any case I am not proposing to change the already chosen trade-off there. Instead, I am proposing that we make the alternative _possible_, and I have a whole set of analyses that are implemented using this alternative waiting to be upstreamed. What about MLIR / other CFGs? ============================= While I personally only work in LLVM IR and MachineIR and my changes only provide the minimum required to ensure that dominator trees continue to work for everything else, the framework is designed with other CFGs in mind. In particular, since `mlir::Value` is poin...

...near scan yet :) The alternatives are either slower at compile time or generate slower code. BTW, the research papers that I mentioned are not about improving register allocation for large blocks (which was the target in the case of BigBlock). They are about register allocation for general purpose CFGs. And they report improvements (greatly reduced number of load/stores for spills) over linear scan. The compilation time is also comparable with linear scan. So, independent of the BigBlock discussion they are worse looking at. > The problem is that bigblock is unmaintained and bitrotted.  Since...

...s is a follow-up on my email from august > (http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-August/042737.html). > > i have, finally, released my OpenCL backend and control-flow > restructuring framework for LLVM (AST-Extractor, or short axtor). The > framework restructures function CFGs such that they can be expressed > entirely without GOTOs or switch/loop-trickery. Hence, making it > possible to emit source-code for strictly control-flow structured > languages (OpenCL, GLSL). The code includes a drop-in OpenCL driver > that > allows source-to-source OpenCL code tr...