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Displaying 3 results from an estimated 3 matches for "cff688d9".

2011 Oct 28
0
[LLVMdev] Itineraries in the powerpc backend
Carter, In my opinion (and I was the one who committed the changes in question), it depends on the hardware. The pipeline descriptions are for the PPC 440, which is an embedded PPC chip use in a variety of places. As such, it is a fairly specific target, and using pipeline-hazard-based scheduling for specific embedded targets is not uncommon. The backends for ARM and MBlaze have similar pipeline
2011 Oct 27
2
[LLVMdev] Itineraries in the powerpc backend
Hello, I was looking over some of the Target commits. I did notice some detailed pipeline descriptions in the ppc backends. I havent noticed anything in the literature describing this technique. Is this a standard approach for mapping SSA to hardware? Thanks in advance, Carter. -------------- next part -------------- An HTML attachment was scrubbed... URL:
2011 Oct 28
2
[LLVMdev] Itineraries in the powerpc backend
...n/listinfo/llvmdev > > -- > Hal Finkel > Postdoctoral Appointee > Leadership Computing Facility > Argonne National Laboratory > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111028/cff688d9/attachment.html>