search for: ceq_cst

...ns! This means that code using > > non-temporal accesses can't rely on LLVM's fence opcode to do the > > right thing, they instead have to rely on architecture-specific > > _mm*fence intrinsics. > > Just for clarify: the proposal to change the implementation of > ceq_cst is arguable separate from this proposal. It will go through > normal patch review once the semantics are addressed. Whatever we > end up doing with ceq_cst, we currently have a semantic hole in our > specification around non-temporals that needs addressed. > Another approach would be t...

Hello, fencing enthusiasts! *TL;DR:* We'd like to propose an addition to the LLVM memory model requiring non-temporal accesses be surrounded by non-temporal load barriers and non-temporal store barriers, and we'd like to add such orderings to the fence IR opcode. We are open to different approaches, hence this email instead of a patch. *Who's "we"?* Philip Reames brought