Displaying 4 results from an estimated 4 matches for "ceecd0e".
2015 Nov 03
3
[PATCH 1/2] disp: activate dual link TMDS links only when possible
...*conf = (ctrl & 0x00000f00) >> 8;
- if (pclk >= 165000)
+ if (pclk >= 165000 && outp->info.duallink_possible)
*conf |= 0x0100;
break;
case DCB_OUTPUT_LVDS:
diff --git a/drm/nouveau/nvkm/engine/disp/nv50.c b/drm/nouveau/nvkm/engine/disp/nv50.c
index 32e73a9..ceecd0e 100644
--- a/drm/nouveau/nvkm/engine/disp/nv50.c
+++ b/drm/nouveau/nvkm/engine/disp/nv50.c
@@ -391,7 +391,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
switch (outp->info.type) {
case DCB_OUTPUT_TMDS:
*conf = (ctrl & 0x00000f00) >> 8;
- if...
2015 Nov 04
1
[PATCH 1/2] disp: activate dual link TMDS links only when possible
...on above.
You mean disp->sor.lvdsconf? What do I do with that? Or did you have
something else in mind?
>
>> break;
>> case DCB_OUTPUT_LVDS:
>> diff --git a/drm/nouveau/nvkm/engine/disp/nv50.c b/drm/nouveau/nvkm/engine/disp/nv50.c
>> index 32e73a9..ceecd0e 100644
>> --- a/drm/nouveau/nvkm/engine/disp/nv50.c
>> +++ b/drm/nouveau/nvkm/engine/disp/nv50.c
>> @@ -391,7 +391,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
>> switch (outp->info.type) {
>> case DCB_O...
2015 Nov 04
0
[PATCH 1/2] disp: activate dual link TMDS links only when possible
...ible)
> *conf |= 0x0100;
I think it might be more robust to key this off the SOR protocol, rather
than duplicating the condition above.
> break;
> case DCB_OUTPUT_LVDS:
> diff --git a/drm/nouveau/nvkm/engine/disp/nv50.c b/drm/nouveau/nvkm/engine/disp/nv50.c
> index 32e73a9..ceecd0e 100644
> --- a/drm/nouveau/nvkm/engine/disp/nv50.c
> +++ b/drm/nouveau/nvkm/engine/disp/nv50.c
> @@ -391,7 +391,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
> switch (outp->info.type) {
> case DCB_OUTPUT_TMDS:
> *conf = (ctrl & 0...
2015 Oct 10
2
[PATCH v2 0/2] drm/nouveau: add support for 2560x1440@56 over HDMI
These patches are adding support for outputting 2560x1440 at 56 over HDMI.
This needs a pixel clock of 225 MHz which was not supported before.
This was tested in a dual monitor setup with a GF114 (GTX 560 TI) and
one HDMI monitor running with 2560x1440 at 56 and one DVI monitor running
with 1920x1200 at 60. This still needs testing on other graphics cards and
with dual link DVI.
There is no