search for: ce1

...is my Problem: I have got a dataframe "a" with various columns. One of those columns is called V3 and contains elements of the following levels: > levels(a$V3) [1] "C" "CA" "CB" "CD" "CD1" "CD2" "CE" "CE1" "CE2" "CE3" "CG" [12] "CG1" "CG2" "CH2" "CZ" "CZ2" "CZ3" "N" "ND1" "ND2" "NE" "NE1" [23] "NE2" "NH1" "NH2" "NZ&quo...

...rdware, so the creation of a software channel does > not apply neither. Perhaps this should be two separate patches? > diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c [...] > + if (device->chipset == 0xea) { > + /* gk20a does not have CE0/CE1 */ This would be another good candidate for a feature flag. > + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; > + arg1 = 1; > + } else > if (device->card_type >= NV_E0) { The formatting here is somewhat weird. From a brief look I couldn't find any indication that nouveau deviates...

...log size = 500000 socket options = TCP_NODELAY SO_RCVBUF=8192 SO_SNDBUF=8192 smb ports = 50139 local master = no domain master = no preferred master = no dns proxy = no printer admin = @printeradmin client schannel = no guest ok = yes log level = 10 workgroup = LAB2003DOMAIN netbios name = ODI-MGT-CE1 wins server = <server ip> password server = <password server ip> security = domain [print$] path = /state/samba/printers guest ok = yes browseable = yes read only = yes write list = @printeradmin force user = root force group = root [printers] comment = All Printers path = /local/...

...rings me to ask: are there any more FIFO engines we somehow missed on Fermi+? There's apparently a new VIC class (0xa0b6), but I've never seen a VIC other than the MCP89 one (0x86b6). AFAICS there's also one unknown enum value in NVRM's FIFO engine enum... (I know of GRAPH, CE0, CE1, CE2, VP1/VP2/MSPDEC, MSRCH/ME, MSPPP, BSP/MSVLD/MSDEC, MPEG, SOFTWARE, CIPHER/SEC, VIC, MSENC). > >> Curiously, a GF116 card that I thought was working fine on nouveau >> actually has 3 for the first engine and 4 for the second. Perhaps it >> just had enough VRAM that I neve...

...ers/gpu/drm/nouveau/nouveau_drm.c index 8d55a50..87bdf04 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -171,6 +171,11 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + if (device->chipset == 0xea) { + /* gk20a does not have CE0/CE1 */ + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; + arg1 = 1; + } else if (device->card_type >= NV_E0) { ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN + 1, @@ -207,6 +212,10 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + /* Need to figure...

...m/nouveau/nouveau_drm.c index ef27949057c3..f2394e84eae6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -171,6 +171,11 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + if (device->chipset == 0xea) { + /* gk20a does not have CE0/CE1 */ + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; + arg1 = 1; + } else if (device->card_type >= NV_E0) { ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN + 1, @@ -207,6 +212,10 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + /* Need to figure...

...s >> not apply neither. > > Perhaps this should be two separate patches? > >> diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c > [...] >> + if (device->chipset == 0xea) { >> + /* gk20a does not have CE0/CE1 */ > > This would be another good candidate for a feature flag. There are ways to query this in a chipset-independent way. However, despite reporting it as an error if no copy engines are available, the code should continue on without the channel happily. Perhaps we can just punt the releve...

Hi Sanjay, Thanks, I saw this flag and it's definitely should be considered, but it appeared to me to be static characteristic of target platform. I'm not sure how appropriate it would be to change its value from a front-end. It says "Has", while optional flag would rather say "Uses" meaning that implementation cares about floating point exceptions. Regards, Sergey

...; } return ConstantVector::get(Result); @@ -1174,15 +1192,17 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, // Given ((a + b) + c), if (b + c) folds to something interesting, return // (a + (b + c)). if (Instruction::isAssociative(Opcode) && CE1->getOpcode() == Opcode) { - Constant *T = ConstantExpr::get(Opcode, CE1->getOperand(1), C2); + Constant *T = ConstantExpr::get(Opcode, CE1->getOperand(1), C2, 0, + nullptr, HonorFPExceptions); if (!isa<ConstantExpr>(T) || cast<...

.... >> >> Perhaps this should be two separate patches? >> >>> diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c >> [...] >>> + if (device->chipset == 0xea) { >>> + /* gk20a does not have CE0/CE1 */ >> >> This would be another good candidate for a feature flag. > There are ways to query this in a chipset-independent way. However, > despite reporting it as an error if no copy engines are available, the > code should continue on without the channel happily. Perhaps we c...

On Mon, Nov 24, 2014 at 8:33 PM, Andy Ritger <aritger at nvidia.com> wrote: > On Fri, Nov 21, 2014 at 01:39:55AM -0500, Ilia Mirkin wrote: >> On Fri, Nov 21, 2014 at 1:16 AM, Andy Ritger <aritger at nvidia.com> wrote: >> > Hi Ilia, >> > >> > Actually 0x90b8 is different than copy engine. I'm not very familiar >> > with it, but 0x90b8 is

...] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGIN...

...] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGIN...

...vdgrspY+W9exuKuXVY9PJR X9fUSAFrymBpCbZArIh0iL0MoAl4O8RaDlKCjREzduGHS5tW2joBW7xfeIxL EGkrCGxLab6KimKvHSJ3j1iIdTNHfwLa4GcAsEg9O9LQaQM6iDCn4ccQAX/T mRzVeSs7qFwWdwoV8+8yHiyeKRw3EQp5NV5dZACP6113gMCyUt6ulA6u2ZT3 ccqx+spIyccgg9olpdCgHY4t8QK/kwNP2C8PSaHh48dXXit34krpvL39U6RD gscn2JV/sNBy2b6nySbRPUEpqIX3hUJh/ce1/WSqirk8Pzj30oVWee9QD3+M q9RQar6Ya1moGUMEo8ah2hJFsWNKjNCh0j1g2lM19xO8Ehqr+MCzFgriGwtd W48qu+ZuvtZu1GpUNR+k3+Yf5dXDXzS1eRNt1PbVrX9yiKVkGap5V8lZyvmp 5AsuFlV3VDrWXaU6rs/2EMxD2E8Z0IOEYGuEU2Z5AbUw0irrwPcTTeZEG5rB iKzXRU4UERzZUZtHn4WRXE1zf5CJege9DhtuJKbbKAsCnPARBUdeZzVdQ6TX ZKxGuvzTEgjXMqcFgLt6OtIu7K0Gtf/...

...] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGIN...

The INA3221 is usually found on mid and high end kepler+ gpus Marins Patch implements the new iccsense subdev and all needed bits for the INA3221 power sensor. My Patch implements the hwmon power1 interface to expose the current power consumption through hwmon (and can be read out via sysfs or the sensors tool) Please test these patches for Fermi+ GPUs, that nothing gets messed up and works as

...NVKM_SUBDEV_NR] = { [NVKM_SUBDEV_THERM ] = "therm", [NVKM_SUBDEV_TIMER ] = "tmr", [NVKM_SUBDEV_VOLT ] = "volt", + [NVKM_SUBDEV_SECBOOT] = "secboot", [NVKM_ENGINE_BSP ] = "bsp", [NVKM_ENGINE_CE0 ] = "ce0", [NVKM_ENGINE_CE1 ] = "ce1", diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index b1ba1c782a2b..95fc9a69d322 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -2092,6 +2092,7 @@ nvkm_device_subdev(struct nvkm_dev...

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via

This is a complete rework from the last version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards, but only the INA3221 bits are tested so far.

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via