Displaying 10 results from an estimated 10 matches for "cctest".
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ctest
2009 Feb 09
2
[LLVMdev] list-td scheduler asserts on targets with implicitly defined registers
...9;s extremely expensive to copy registers
> in the particular register class.
Evan,
I am not sure what you mean by "if you just want a check" - I was trying to point out that for example the following very simple testcase makes llc -march=x86 -pre-RA-sched=list-td crash :
define i32 @cctest(i32 %a, i32 %b) nounwind readnone {
entry:
%not. = icmp sge i32 %a, %b ; <i1> [#uses=1]
%.0 = zext i1 %not. to i32 ; <i32> [#uses=1]
ret i32 %.0
}
The assert() which triggers has been introduced since llvm 2.4.
So I assume that (at least...
2017 Nov 14
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...location-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -fuse-init-array -target-cpu generic -target-feature +neon -target-abi aapcs -fallow-half-arguments-and-returns -dwarf-column-info -debugger-tuning=gdb -coverage-notes-file /work/innovation/cctest/test.gcno -resource-dir /work/llvm/build/lib/clang/6.0.0 -O0 -fdebug-compilation-dir /work/innovation/cctest -ferror-limit 19 -fmessage-length 226 -fno-signed-char -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -mllvm -global-isel -mllvm -global-isel-abort=0 -o test.o -x c test.c...
2017 Nov 14
6
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...location-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -fuse-init-array -target-cpu generic -target-feature +neon -target-abi aapcs -fallow-half-arguments-and-returns -dwarf-column-info -debugger-tuning=gdb -coverage-notes-file /work/innovation/cctest/test.gcno -resource-dir /work/llvm/build/lib/clang/6.0.0 -O0 -fdebug-compilation-dir /work/innovation/cctest -ferror-limit 19 -fmessage-length 226 -fno-signed-char -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -mllvm -global-isel -mllvm -global-isel-abort=0 -o test.o -x c test.c...
2009 Feb 06
0
[LLVMdev] list-td scheduler asserts on targets with implicitly defined registers
The best fix is to teach this scheduler how to deal with these
dependencies. :-)
If you just want a check, I think it's easier to just check register
class's copy cost. -1 means it's extremely expensive to copy registers
in the particular register class.
Evan
On Feb 6, 2009, at 2:22 AM, Christian Sayer wrote:
> Hi,
>
> I just switched to the 2.5 release branch and
2017 Nov 17
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...location-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -fuse-init-array -target-cpu generic -target-feature +neon -target-abi aapcs -fallow-half-arguments-and-returns -dwarf-column-info -debugger-tuning=gdb -coverage-notes-file /work/innovation/cctest/test.gcno -resource-dir /work/llvm/build/lib/clang/6.0.0 -O0 -fdebug-compilation-dir /work/innovation/cctest -ferror-limit 19 -fmessage-length 226 -fno-signed-char -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -mllvm -global-isel -mllvm -global-isel-abort=0 -o test.o -x c test.c...
2017 Nov 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...location-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -fuse-init-array -target-cpu generic -target-feature +neon -target-abi aapcs -fallow-half-arguments-and-returns -dwarf-column-info -debugger-tuning=gdb -coverage-notes-file /work/innovation/cctest/test.gcno -resource-dir /work/llvm/build/lib/clang/6.0.0 -O0 -fdebug-compilation-dir /work/innovation/cctest -ferror-limit 19 -fmessage-length 226 -fno-signed-char -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -mllvm -global-isel -mllvm -global-isel-abort=0 -o test.o -x c test.c...
2009 Feb 06
2
[LLVMdev] list-td scheduler asserts on targets with implicitly defined registers
Hi,
I just switched to the 2.5 release branch and noticed that llc runs into the following assert in ScheduleDAGList::ScheduleNodeTopDown() using our custom backend:
assert(!I->isAssignedRegDep() &&
"The list-td scheduler doesn't yet support physreg dependencies!");
It turns out that the register dependency concerns the condition code register which is
2005 Nov 21
5
question about disk performance in domU
Hi all,
When I ran the experiments to compare an application''s execution time in both a domU (named cctest1)
and a native Linux machine (named ccn10), I noticed the application executes faster in domU. The
host of the domU (named ccn9) and ccn10 are two nodes of a cluster and they have same hardware
configurations. domU (cctest1) is created by exporting loopback files from dom0 on ccn9 as VBD
backen...
2005 Nov 21
0
question about disk performance in domU
Hi all,
When I ran the experiments to compare an application''s execution time in both a domU (named cctest1)
and a native Linux machine (named ccn10), I noticed the application executes faster in domU. The
host of the domU (named ccn9) and ccn10 are two nodes of a cluster and they have same hardware
configurations. domU (cctest1) is created by exporting loopback files from dom0 on ccn9 as VBD
backen...
2017 Nov 13
3
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin,
My only remaining concern is around ABI compatibility.
The following commit seems to indicate that in the previous round of evaluation, we didn’t find an existing ABI compatibility issue:
http://llvm.org/viewvc/llvm-project?view=revision&revision=311388.
I haven’t looked into the details of this issue - so maybe I’m worried over nothing?
I’m wondering if since then on your side