Displaying 3 results from an estimated 3 matches for "ccd6e28c".
Did you mean:
c7d6e24c
2013 Jul 16
0
[LLVMdev] Operand constrain specification
----- Original Message -----
>
>
> Hi,
>
> How can I specify in a .td file that source and destination should
> not use the same register?
I think that you can use the EarlyClobber operand flag to achieve this (TableGen has an @earlyclobber constraint; there are some examples in the ARM backend).
-Hal
>
> Thanks.
>
>
> * Elena
>
>
>
>
2013 Jul 16
3
[LLVMdev] Operand constrain specification
Hi,
How can I specify in a .td file that source and destination should not use the same register?
Thanks.
- Elena
---------------------------------------------------------------------
Intel Israel (74) Limited
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If
2013 Jul 16
1
[LLVMdev] Operand constrain specification
...___
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130716/ccd6e28c/attachment.html>