search for: cc10

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2019 Jul 16
2
Custom calling convention & ARM target
Hello. For our project needs we implemented a custom calling convention. The main goals are to pass function arguments in registers and always use tailcall optimization for calls to functions with our CC when applicable. Function arguments are always pointers and the maximum number of arguments is 5. No frame pointer register is in use for this CC. No varargs. Finally, there are not any
2019 Jul 17
2
Custom calling convention & ARM target
...a Raspberry Pi 3 device. Yes, changing the triple to armv7-unknown-linux-gnueabi changes the emitted return instruction to 'bx lr'. But this is not the issue. Let me describe it based on an example I prepared to demonstrate the problem. Currently, LLVM contains GHC calling convention (aka cc10) and this CC is very similar to what we are trying to implement. The difference is that our CC has a simpler argument specification (only pointers) and could have a prologue/epilogue. I wrote a simple example which is a sort of interpreter implemented as a threaded code. The C version of it is here...
2013 Aug 02
0
[LLVMdev] Tail calls (TCO) in PNaCL | PNaCl Bitcode reference manual
...i32 @callee(i32 %a1, i32 0) ret i32 %1 } That results in a call rather than a jmp. You won't get a jmp back unless you write: declare fastcc i32 @callee(i32, i32) define fastcc i32 @caller(i32 %a1) { %1 = tail call fastcc i32 @callee(i32 %a1, i32 0) ret i32 %1 } (Or use cc10 rather than fastcc.) You can even break the tail call elimination by simply passing a value not in the caller's incoming argument stack (or one in the wrong position), again on x86-32: declare i32 @callee(i32) define i32 @caller(i32 %a1) { %a = add i32 %a1, %a1 %1 = tail call i32...
2013 Aug 02
2
[LLVMdev] Tail calls (TCO) in PNaCL | PNaCl Bitcode reference manual
On 1 August 2013 00:11, Travis Cross <tc at travislists.com> wrote: > On 2013-07-30 22:11, Eli Bendersky wrote: > > we've published an initial version of the PNaCl bitcode reference > > manual online - > > http://www.chromium.org/nativeclient/pnacl/bitcode-abi. The PNaCl > > bitcode is a restricted subset of LLVM IR. > > > > Any comments would be