Displaying 9 results from an estimated 9 matches for "cb_bind".
2016 Oct 16
0
[PATCH 2/5] nvc0: make use of the new hwdefs for TEX_CB_INDEX
...| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 52a17db..0682806 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -313,7 +313,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0x00000001);
BEGIN_NVC0(push, NVC0_3D(CB_BIND(4)), 1);
PUSH_DATA (push, 0x11);
- BEGIN_NVC0(push, SUBC_3D(0x2608), 1);
+ BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
PUSH_DATA (push, 1);
}
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 4c3bb0f..607e97b 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -12,6 +12,7 @@
/...
2014 Nov 19
5
[PATCH v2 0/3] nouveau: support for custom VRAM domains
This series is to allow NVIDIA chips with shared memory to operate more
efficiently (and to operate at all once we disable VRAM from the kernel
driver) by allowing nouveau_screen to specify a domain to use for objects
originally allocated into VRAM. If the domain is not overridden, the default
NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be
used in place of
2014 Nov 19
0
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...vc0/nvc0_state_validate.c
index 25a3232b48d9..696eacaa1e20 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
@@ -439,7 +439,7 @@ nvc0_constbufs_validate(struct nvc0_context *nvc0)
BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
PUSH_DATA (push, (0 << 4) | 1);
}
- nvc0_cb_push(&nvc0->base, bo, NOUVEAU_BO_VRAM,
+ nvc0_cb_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
base, nvc0->state.uniform_bu...
2014 Nov 19
1
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...> index 25a3232b48d9..696eacaa1e20 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
> @@ -439,7 +439,7 @@ nvc0_constbufs_validate(struct nvc0_context *nvc0)
> BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
> PUSH_DATA (push, (0 << 4) | 1);
> }
> - nvc0_cb_push(&nvc0->base, bo, NOUVEAU_BO_VRAM,
> + nvc0_cb_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
> bas...
2014 Nov 19
1
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...> index 25a3232b48d9..696eacaa1e20 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
> @@ -439,7 +439,7 @@ nvc0_constbufs_validate(struct nvc0_context *nvc0)
> BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
> PUSH_DATA (push, (0 << 4) | 1);
> }
> - nvc0_cb_push(&nvc0->base, bo, NOUVEAU_BO_VRAM,
> + nvc0_cb_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
> base,...
2014 Oct 27
4
[PATCH 0/3] nouveau: support for custom VRAM domains
This series is to allow NVIDIA chips with shared memory to operate more
efficiently (and to operate at all once we disable VRAM from the kernel
driver) by allowing nouveau_screen to specify a domain to use for objects
originally allocated into VRAM. If the domain is not overridden, the default
NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be
used in place of
2015 Jun 19
5
[PATCH v3 0/2] nouveau: support for custom VRAM domains
New revision of this patchset that prevents VRAM objects from being
allocated on VRAM-less systems like Tegra. This is required for Mesa
to work on such systems.
Changes since v2:
- Use vram_size to detect systems without VRAM and set the correct
domain instead of expecting each chip to set its domain explicitly.
Alexandre Courbot (2):
nouveau: support for custom VRAM domains
nvc0: use
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
...0x20*(i0))
+#define NVE4_3D_UNK2400_TSC2__ESIZE 0x00000020
+#define NVE4_3D_UNK2400_TSC2__LEN 0x00000005
+
+#define NVE4_3D_UNK2400_TIC2(i0) (0x0000240c + 0x20*(i0))
+#define NVE4_3D_UNK2400_TIC2__ESIZE 0x00000020
+#define NVE4_3D_UNK2400_TIC2__LEN 0x00000005
+
#define NVC0_3D_CB_BIND(i0) (0x00002410 + 0x20*(i0))
#define NVC0_3D_CB_BIND__ESIZE 0x00000020
#define NVC0_3D_CB_BIND__LEN 0x00000005
@@ -1778,6 +1888,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_VERT_COLOR_CLAMP_EN 0x00002600
+#define NVE4_3D_UNK2604...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update