search for: cap_vndr

...ot; +#endif #define VIRTIO_PCI_HOST_FEATURES VIRTIO_PCI_LEGACY_HOST_FEATURES #define VIRTIO_PCI_GUEST_FEATURES VIRTIO_PCI_LEGACY_GUEST_FEATURES #define VIRTIO_PCI_QUEUE_PFN VIRTIO_PCI_LEGACY_QUEUE_PFN @@ -125,10 +127,10 @@ /* This is the PCI capability header: */ struct virtio_pci_cap { - u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ - u8 cap_next; /* Generic PCI field: next ptr. */ - u8 cfg_type; /* One of the VIRTIO_PCI_CAP_*_CFG. */ - u8 bar; /* Where to find it. */ + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 c...

...ot; +#endif #define VIRTIO_PCI_HOST_FEATURES VIRTIO_PCI_LEGACY_HOST_FEATURES #define VIRTIO_PCI_GUEST_FEATURES VIRTIO_PCI_LEGACY_GUEST_FEATURES #define VIRTIO_PCI_QUEUE_PFN VIRTIO_PCI_LEGACY_QUEUE_PFN @@ -125,10 +127,10 @@ /* This is the PCI capability header: */ struct virtio_pci_cap { - u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ - u8 cap_next; /* Generic PCI field: next ptr. */ - u8 cfg_type; /* One of the VIRTIO_PCI_CAP_*_CFG. */ - u8 bar; /* Where to find it. */ + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 c...

...*/ +#define VIRTIO_PCI_CAP_COMMON_CFG 1 +/* Notifications */ +#define VIRTIO_PCI_CAP_NOTIFY_CFG 2 +/* ISR access */ +#define VIRTIO_PCI_CAP_ISR_CFG 3 +/* Device specific confiuration */ +#define VIRTIO_PCI_CAP_DEVICE_CFG 4 + +/* This is the PCI capability header: */ +struct virtio_pci_cap { + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 cap_len; /* Generic PCI field: capability length */ + __u8 type_and_bar; /* Upper 3 bits: bar. + * Lower 3 is VIRTIO_PCI_CAP_*_CFG. */ + __le32 offset; /* Offset within bar. */ + __le32 leng...

...-------- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index 4e05423..a2b2e13 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -117,10 +117,11 @@ struct virtio_pci_cap { __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ __u8 cap_next; /* Generic PCI field: next ptr. */ __u8 cap_len; /* Generic PCI field: capability length */ - __u8 type_and_bar; /* Upper 3 bits: bar. - * Lower 3 is VIRTIO_PCI_CAP_*_CFG. */ + __u8 cfg_type; /* Identifies the structure. */ + __u8...

...*/ +#define VIRTIO_PCI_CAP_COMMON_CFG 1 +/* Notifications */ +#define VIRTIO_PCI_CAP_NOTIFY_CFG 2 +/* ISR access */ +#define VIRTIO_PCI_CAP_ISR_CFG 3 +/* Device specific confiuration */ +#define VIRTIO_PCI_CAP_DEVICE_CFG 4 + +/* This is the PCI capability header: */ +struct virtio_pci_cap { + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 cap_len; /* Generic PCI field: capability length */ + __u8 type_and_bar; /* Upper 3 bits: bar. + * Lower 3 is VIRTIO_PCI_CAP_*_CFG. */ + __le32 offset; /* Offset within bar. */ + __le32 leng...

...-------- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index 4e05423..a2b2e13 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -117,10 +117,11 @@ struct virtio_pci_cap { __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ __u8 cap_next; /* Generic PCI field: next ptr. */ __u8 cap_len; /* Generic PCI field: capability length */ - __u8 type_and_bar; /* Upper 3 bits: bar. - * Lower 3 is VIRTIO_PCI_CAP_*_CFG. */ + __u8 cfg_type; /* Identifies the structure. */ + __u8...

...i/linux/virtio_pci.h index 28c2ce0..5d546c6 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -159,6 +159,36 @@ struct virtio_pci_common_cfg { __le32 queue_used_hi; /* read-write */ }; +/* Macro versions of offsets for the Old Timers! */ +#define VIRTIO_PCI_CAP_VNDR 0 +#define VIRTIO_PCI_CAP_NEXT 1 +#define VIRTIO_PCI_CAP_LEN 2 +#define VIRTIO_PCI_CAP_TYPE_AND_BAR 3 +#define VIRTIO_PCI_CAP_OFFSET 4 +#define VIRTIO_PCI_CAP_LENGTH 8 + +#define VIRTIO_PCI_NOTIFY_CAP_MULT 12 + +#define VIRTIO_PCI_COMMON_DFSELECT 0 +#define VIRTIO_PCI_COMMON_DF 4 +#define VIR...

...i/linux/virtio_pci.h index 28c2ce0..5d546c6 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -159,6 +159,36 @@ struct virtio_pci_common_cfg { __le32 queue_used_hi; /* read-write */ }; +/* Macro versions of offsets for the Old Timers! */ +#define VIRTIO_PCI_CAP_VNDR 0 +#define VIRTIO_PCI_CAP_NEXT 1 +#define VIRTIO_PCI_CAP_LEN 2 +#define VIRTIO_PCI_CAP_TYPE_AND_BAR 3 +#define VIRTIO_PCI_CAP_OFFSET 4 +#define VIRTIO_PCI_CAP_LENGTH 8 + +#define VIRTIO_PCI_NOTIFY_CAP_MULT 12 + +#define VIRTIO_PCI_COMMON_DFSELECT 0 +#define VIRTIO_PCI_COMMON_DF 4 +#define VIR...

...pci.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index cda688f..a5ef8cd 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -129,6 +129,7 @@ struct virtio_pci_cap { __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 cap_len; /* Generic PCI field: capability length */ __u8 cfg_type; /* One of the VIRTIO_PCI_CAP_*_CFG. */ __u8 bar; /* Where to find it. */ __le32 offset; /* Offset within bar. */ @@ -154,7 +...

...e VIRTIO_PCI_CAP_NOTIFY_CFG 2 +/* ISR access */ +#define VIRTIO_PCI_CAP_ISR_CFG 3 +/* Device specific configuration */ +#define VIRTIO_PCI_CAP_DEVICE_CFG 4 +/* PCI configuration access */ +#define VIRTIO_PCI_CAP_PCI_CFG 5 + +/* This is the PCI capability header: */ +struct virtio_pci_cap { + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 cap_len; /* Generic PCI field: capability length */ + __u8 cfg_type; /* Identifies the structure. */ + __u8 bar; /* Where to find it. */ + __u8 padding[3]; /* Pad to full dword. */ + __le32 off...

...e VIRTIO_PCI_CAP_NOTIFY_CFG 2 +/* ISR access */ +#define VIRTIO_PCI_CAP_ISR_CFG 3 +/* Device specific configuration */ +#define VIRTIO_PCI_CAP_DEVICE_CFG 4 +/* PCI configuration access */ +#define VIRTIO_PCI_CAP_PCI_CFG 5 + +/* This is the PCI capability header: */ +struct virtio_pci_cap { + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 cap_len; /* Generic PCI field: capability length */ + __u8 cfg_type; /* Identifies the structure. */ + __u8 bar; /* Where to find it. */ + __u8 padding[3]; /* Pad to full dword. */ + __le32 off...

Based on Rusty's patches. Coding style and funny jokes are his. Bugs and a star wars reference (should be easy to spot) are mine. Untested, but useful as basis for beginning the qemu work. TODO: = simplify probing: use a common probe function, probe with modern driver first, if that fails - probe with legacy driver. BUGS: ATM legacy driver can win and drive a transitional device

Based on Rusty's patches. Coding style and funny jokes are his. Bugs and a star wars reference (should be easy to spot) are mine. Untested, but useful as basis for beginning the qemu work. TODO: = simplify probing: use a common probe function, probe with modern driver first, if that fails - probe with legacy driver. BUGS: ATM legacy driver can win and drive a transitional device

This is just the full patchset reposted with fixups in correct order, before squashing them. I also tweaked commit log for patch "virtio_pci: modern driver" I also included Gerd's tag: Tested-by: Gerd Hoffmann <kraxel at redhat.com> You can find it all before the rebase -i --autosquash in my tree: git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git virtio-next

This is just the full patchset reposted with fixups in correct order, before squashing them. I also tweaked commit log for patch "virtio_pci: modern driver" I also included Gerd's tag: Tested-by: Gerd Hoffmann <kraxel at redhat.com> You can find it all before the rebase -i --autosquash in my tree: git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git virtio-next

...+ > + while (pos) { > + ret = ifcvf_read_config_range(dev, (u32 *)&cap, > + sizeof(cap), pos); > + > + if (ret < 0) { > + IFC_ERR(&dev->dev, "Failed to get PCI capability at %x", > + pos); > + break; > + } > + > + if (cap.cap_vndr != PCI_CAP_ID_VNDR) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + c...

...+ > + while (pos) { > + ret = ifcvf_read_config_range(dev, (u32 *)&cap, > + sizeof(cap), pos); > + > + if (ret < 0) { > + IFC_ERR(&dev->dev, "Failed to get PCI capability at %x", > + pos); > + break; > + } > + > + if (cap.cap_vndr != PCI_CAP_ID_VNDR) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + c...

...+ > + while (pos) { > + ret = ifcvf_read_config_range(dev, (u32 *)&cap, > + sizeof(cap), pos); > + > + if (ret < 0) { > + IFC_ERR(&dev->dev, "Failed to get PCI capability at %x", > + pos); > + break; > + } > + > + if (cap.cap_vndr != PCI_CAP_ID_VNDR) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + c...

...+ > + while (pos) { > + ret = ifcvf_read_config_range(dev, (u32 *)&cap, > + sizeof(cap), pos); > + > + if (ret < 0) { > + IFC_ERR(&dev->dev, "Failed to get PCI capability at %x", > + pos); > + break; > + } > + > + if (cap.cap_vndr != PCI_CAP_ID_VNDR) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + c...

...> + > + while (pos) { > + ret = ifcvf_read_config_range(dev, (u32 *)&cap, > + sizeof(cap), pos); > + > + if (ret < 0) { > + IFC_ERR(&dev->dev, "failed to get PCI capability at %x", > + pos); > + break; > + } > + > + if (cap.cap_vndr != PCI_CAP_ID_VNDR) > + goto next; > + > + IFC_INFO(&dev->dev, "read PCI config:\n" > + "config type: %u.\n" > + "PCI bar: %u.\n" > + "PCI bar offset: %u.\n" > + "PCI config len: %u.\n", > + cap....