Displaying 9 results from an estimated 9 matches for "canrealignstack".
2013 Nov 21
2
[LLVMdev] Unaligned load/store for callee-saved 128-bit registers
...g?
> > >
> >
> > This looks like a bug. By default, isStackRealignable() always
> > returns true (this default comes from the TargetFrameLowering
> > constructor). I wonder, however, is this is not correctly
> > implemented in some backends (X86RegisterInfo::canRealignStack, for
> > example, is not completely trivial). Nadav, do you know how this
> > works?
>
> [Trying some other relevant people...]
>
> Chad, Jakob: thoughts?
>
> -Hal
>
>
>
> >
> > -Hal
> >
> > >
> > > Thanks,
> >...
2013 Nov 21
2
[LLVMdev] Unaligned load/store for callee-saved 128-bit registers
...a bug or am I missing something?
> >
>
> This looks like a bug. By default, isStackRealignable() always
> returns true (this default comes from the TargetFrameLowering
> constructor). I wonder, however, is this is not correctly
> implemented in some backends (X86RegisterInfo::canRealignStack, for
> example, is not completely trivial). Nadav, do you know how this
> works?
[Trying some other relevant people...]
Chad, Jakob: thoughts?
-Hal
>
> -Hal
>
> >
> > Thanks,
> > Francois Pichet, Octasic.
> >
> > _______________________________...
2013 Nov 18
0
[LLVMdev] Unaligned load/store for callee-saved 128-bit registers
...ackAlign);
>
> Is this a bug or am I missing something?
>
This looks like a bug. By default, isStackRealignable() always returns true (this default comes from the TargetFrameLowering constructor). I wonder, however, is this is not correctly implemented in some backends (X86RegisterInfo::canRealignStack, for example, is not completely trivial). Nadav, do you know how this works?
-Hal
>
> Thanks,
> Francois Pichet, Octasic.
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http:/...
2013 Nov 18
2
[LLVMdev] Unaligned load/store for callee-saved 128-bit registers
On my (out-of-tree) target I have 16 128-bit registers.
Unaligned load/store are illegal. (must 16-bytes aligned)
8 of those registers are defined as callee-saved and 8 caller-saved.
The default stack size is 4 bytes.
The target implements dynamic stack realign to make sure the stack will
always be aligned correctly when necessary.
Yet I am still getting unaligned load/store when running this
2013 Nov 21
0
[LLVMdev] Unaligned load/store for callee-saved 128-bit registers
...ing?
> > >
> >
> > This looks like a bug. By default, isStackRealignable() always
> > returns true (this default comes from the TargetFrameLowering
> > constructor). I wonder, however, is this is not correctly
> > implemented in some backends (X86RegisterInfo::canRealignStack, for
> > example, is not completely trivial). Nadav, do you know how this
> > works?
>
> [Trying some other relevant people...]
>
> Chad, Jakob: thoughts?
>
> -Hal
>
> >
> > -Hal
> >
> > >
> > > Thanks,
> > > Francois P...
2012 Mar 01
0
[LLVMdev] LLVMdev Digest, Vol 93, Issue 3
...efault stack
> alignment is 128bit and LLVM doesn't adjust it automatically?
>
> Joerg
>
Hey Joerg,
The faulty code can be found in
function X86InstrInfo::storeRegToStackSlot(...)
from /lib/Target/X86/X86InstrInfo.cpp.
> bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
When creating the spill's machine instruction, the spill slot is assumed to
be aligned if the alignment is >= 16 bytes, which is not the case for AVX.
AVX spills require 32 byte alignment to make use of aligned moves. The
stack is not adjusted automatically.
For performance, the best...
2012 Mar 01
3
[LLVMdev] Stack alignment on X86 AVX seems incorrect
Even if you explicitly specify –stack-alignment=16 the aligned movs are still generated.
It is not an issue related to ABI.
See my original mail:
./llc -mattr=+avx -stack-alignment=16 < basic.ll | grep movaps | grep ymm | grep rbp
vmovaps -176(%rbp), %ymm14
vmovaps -144(%rbp), %ymm11
vmovaps -240(%rbp), %ymm13
- Elena
From: Cameron McInally
2015 Apr 21
2
[LLVMdev] question about alignment of structures on the stack (arm 32)
Hello Tim, thanks for response
----------------------------------------
> Date: Mon, 20 Apr 2015 11:45:03 -0700
> Subject: Re: [LLVMdev] question about alignment of structures on the stack (arm 32)
> From: t.p.northover at gmail.com
> To: alexey.perevalov at hotmail.com
> CC: llvmdev at cs.uiuc.edu
>
> On 20 April 2015 at 11:09, Alexey Perevalov
> <alexey.perevalov at
2015 Apr 23
2
[LLVMdev] question about alignment of structures on the stack (arm 32)
...or example
- subq $32, %rsp
+ andq $-8, %rsp
+ subq $24, %rsp
...
and of course modified function body,
but for arm nothing happened. I tried to understand what goes wrong in llvm, but too many layers of abstractions.
Maybe that code exists, but condition from ARMBaseRegisterInfo::canRealignStack prevent its generation.
BTW, I build llvm/clang 3.6 (it was impossible to build latest version from HEAD ) and something changed ;)
- str r1, [sp, #20]
- str r2, [sp, #16]
- add r1, sp, #16
- orr r2, r1, #4
+ str r1, [sp, #16]
+ str r2, [sp, #12]
+ add r...