Displaying 5 results from an estimated 5 matches for "callv3".
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call3
2012 Aug 17
0
[LLVMdev] Assert in LiveInterval update
...e HexagonMachineScheduler.cpp
== MachineScheduler.cpp and VLIWMachineScheduler == ScheduleDAGMI
The instruction being moved is a simple call:
let isCall = 1, neverHasSideEffects = 1,
Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
P0, P1, P2, P3, LC0, LC1, SA0, SA1, USR] in {
def CALLv3 : JInst<(outs), (ins calltarget:$dst),
"call $dst", []>, Requires<[HasV3T]>;
}
CALLv3 <ga:@printf>, %D0<imp-def,dead>, %D1<imp-def,dead>,
%D2<imp-def,dead>, %R31<imp-def>, %R0<imp-use,kill>, ...
Another clue - slot renumbering...
2012 Aug 15
3
[LLVMdev] MI bundle liveness attributes
On Aug 13, 2012, at 8:34 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> Andy,
>
> Yes, this is what Arnold has suggested also, and from this point it looks
> like it should work, but it will require parsing the bundle every time we
> care to know whether this is a real use or a conditional def. This might
> become awkward... but I guess I should provide a better
2013 Jan 14
2
[LLVMdev] Splitting live ranges of half-defined registers
...ead-undef> = ADDri_SUBr_V4 %vreg62,
5, %vreg61; DoubleRegs:%vreg304 IntRegs:%vreg62,%vreg61
%vreg519<def> = TFRI 3148; IntRegs:%vreg519
%vreg523<def> = TFRI64 15; DoubleRegs:%vreg523
%R0<def> = COPY %vreg304:subreg_loreg; DoubleRegs:%vreg304
CALLv3 <ga:@foo>, %D0<imp-def,dead>, %D1<imp-def,dead>,
%D2<imp-def,dead>, %R31<imp-def>, %R0<imp-use>, %R1<imp-use>,
%R0<imp-def>, ...
Then, after live range splitting, we have vreg539 and vreg537, and right
before the call, a copy from half-undefined...
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
...uler.cpp and
> VLIWMachineScheduler == ScheduleDAGMI
>
>
> The instruction being moved is a simple call:
>
> let isCall = 1, neverHasSideEffects = 1,
> Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
> P0, P1, P2, P3, LC0, LC1, SA0, SA1, USR] in {
> def CALLv3 : JInst<(outs), (ins calltarget:$dst),
> "call $dst", []>, Requires<[HasV3T]>; }
>
> CALLv3 <ga:@printf>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-
> def,dead>, %R31<imp-def>, %R0<imp-use,kill>, ...
>
>...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...; -def : Pat<(call IntRegs:$dst),
>> - (CALLRv3 IntRegs:$dst)>, Requires<[HasV3T]>;
>> +def : Pat<(call (i32 IntRegs:$dst)),
>> + (CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
>> def : Pat<(call tglobaladdr:$dst),
>> (CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
>> def : Pat<(call texternalsym:$dst),
>> diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td
>> index 9e60cf2..f507e4f 100644
>> --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td...