search for: callseq

Displaying 16 results from an estimated 16 matches for "callseq".

2013 Mar 01
4
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_1; > > mov.f64 %fl1, > > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_2; > > mov.f64 %fl0, > > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_3; > > // Callseq Start 0 > > { > > .reg .b32 temp_param_reg; > > // <end>} > > .reg .b32 retval0; > > call.uni (retval0), > > INT_PTX_SREG_CTAID_X, > > ( &g...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...> > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_1; > > > mov.f64 %fl1, > > > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_2; > > > mov.f64 %fl0, > > > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_3; > > > // Callseq Start 0 > > > { > > > .reg .b32 temp_param_reg; > > > // <end>} > > > .reg .b32 retval0; > > > call.uni (retval0), > > > INT_PTX_SREG_CTAID_X, > > > ( > > > ); > > > mov.b32 %r0, retval0; > > > > &gt...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...D_mandelbrot_2D_ptx_param_1; >> > mov.f64 %fl1, >> > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_2; >> > mov.f64 %fl0, >> > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_3; >> > // Callseq Start 0 >> > { >> > .reg .b32 temp_param_reg; >> > // <end>} >> > .reg .b32 retval0; >> > call.uni (retval0), >> > INT_PTX_SREG_CTAID_X, >&g...
2013 Mar 01
1
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
..._1; > >> > mov.f64 %fl1, > >> > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_2; > >> > mov.f64 %fl0, > >> > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_3; > >> > // Callseq Start 0 > >> > { > >> > .reg .b32 temp_param_reg; > >> > // <end>} > >> > .reg .b32 retval0; > >> > call.uni (retval0), > >> >...
2013 Mar 01
2
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...t_2F_calc_2D_mandelbrot_2D_ptx_param_0; mov.f64 %fl2, examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_1; mov.f64 %fl1, examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_2; mov.f64 %fl0, examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_3; // Callseq Start 0 { .reg .b32 temp_param_reg; // <end>} .reg .b32 retval0; call.uni (retval0), INT_PTX_SREG_CTAID_X, ( ); mov.b32 %r0, retval0; //{ }// Callseq End 0 // Callseq Start 1 { .re...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...4 %fl2, > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_1; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64 %fl1, > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_2; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64 %fl0, > examples_2E_mandelbrot_2F_calc_2D_mandelbrot_2D_ptx_param_3; >聽 聽 聽 聽 聽 聽 聽 聽 // Callseq Start 0 >聽 聽 聽 聽 聽 聽 聽 聽 { >聽 聽 聽 聽 聽 聽 聽 聽 .reg .b32 temp_param_reg; >聽 聽 聽 聽 聽 聽 聽 聽 // <end>} >聽 聽 聽 聽 聽 聽 聽 聽 .reg .b32 retval0; >聽 聽 聽 聽 聽 聽 聽 聽 call.uni (retval0), >聽 聽 聽 聽 聽 聽 聽 聽 INT_PTX_SREG_CTAID_X, >聽 聽 聽 聽 聽 聽 聽 聽 ( >聽 聽 聽 聽 聽 聽 聽 聽 ); >聽 聽 聽 聽 聽...
2015 Jan 19
2
[LLVMdev] [INCOMPLETE] [GC] Support wrapping vararg functions in statepoint
...lue of the call iff any. const bool HasDef = !Tmp->getType()->isVoidTy(); @@ -275,10 +278,10 @@ static SDNode *lowerCallFromStatepoint(const CallInst &CI, // We just emitted a call, so it should be last thing generated SDValue Chain = Builder.DAG.getRoot(); - - // Find closest CALLSEQ_END walking back through lowered nodes if needed SDNode *CallEnd = Chain.getNode(); int Sanity = 0; + + // Find closest CALLSEQ_END walking back through lowered nodes if needed while (CallEnd->getOpcode() != ISD::CALLSEQ_END) { CallEnd = CallEnd->getGluedNode(); assert(Cal...
2009 Dec 08
0
[LLVMdev] PR 5723
Hello, David > For X86 CALLSEQ_START gets selected to ADJCALLSTACKDOWN or > ADJCALLSTACKDOWN64 in this case.  So is CALLSEQ_START expected > to appear only once (at the top of the function)?  The comments > are rather confusing.  It seems like CALLSEQ_START is supposed > to appear before every call, but surely there&...
2007 Apr 24
0
[LLVMdev] (no subject)
Hi, During isel lowering, the backend insertes CALLSEQ_START / CALLSEQ_END target independent nodes to the DAG. These are then selected to X86 specific instructions ADJCALLSTACKDOWN / ADJCALLSTACKUP. At these point, they have a constant arguments which corresponds to the fixed frame size for argument passing. But the size of the stack frame i...
2018 May 04
0
How to constraint instructions reordering from patterns?
...418>)> t24:1, GlobalAddress:i16<float* @x3> 0, undef:i16 t26: f32,ch = load<Volatile LD4[@x4](tbaa=<0x3dbe418>)> t25:1, GlobalAddress:i16<float* @x4> 0, undef:i16 t27: i16 = GlobalAddress<float (float, float, float, float)* @fdivfaddfmul_a> 0 t29: ch,glue = callseq_start t26:1, TargetConstant:i16<4> t31: ch,glue = CLPISD::COPY_TO_CALLEE_A t29, t23, FrameIndex:i16<0>, t29:1 t33: ch,glue = CLPISD::COPY_TO_CALLEE_A t31, t24, FrameIndex:i16<1>, t31:1 t35: ch,glue = CLPISD::COPY_TO_CALLEE_A t33, t25, FrameIndex:i16<2>, t33:1 t37: ch...
2009 Dec 08
2
[LLVMdev] PR 5723
...ind > anywhere in the sources or generated files where that opcode is set. > I believe we need to generate that instruction if it does not exist > (along with CallFrameDestroyOpcode) in the presence of TLS, at least > on X86 where's it's implemented via a function call. For X86 CALLSEQ_START gets selected to ADJCALLSTACKDOWN or ADJCALLSTACKDOWN64 in this case. So is CALLSEQ_START expected to appear only once (at the top of the function)? The comments are rather confusing. It seems like CALLSEQ_START is supposed to appear before every call, but surely there's only one sta...
2007 Apr 24
2
[LLVMdev] (no subject)
Hello, I am trying to add an instruction before each function call to add/ subtract the stack pointer by a value specified at the command line. I wonder if I can do that during lowering. For example, in X86TargetLowering::LowerCALL. I appreciate it if you give me some hints how and where I can do that. Thank you, Babak
2018 May 04
2
How to constraint instructions reordering from patterns?
...@x3> 0, undef:i16 > >   t26: f32,ch = load<Volatile LD4[@x4](tbaa=<0x3dbe418>)> t25:1, > GlobalAddress:i16<float* @x4> 0, undef:i16 > >   t27: i16 = GlobalAddress<float (float, float, float, float)* > @fdivfaddfmul_a> 0 > >   t29: ch,glue = callseq_start t26:1, TargetConstant:i16<4> > >   t31: ch,glue = CLPISD::COPY_TO_CALLEE_A t29, t23, FrameIndex:i16<0>, > t29:1 > >   t33: ch,glue = CLPISD::COPY_TO_CALLEE_A t31, t24, FrameIndex:i16<1>, > t31:1 > >   t35: ch,glue = CLPISD::COPY_TO_CALLEE_A t3...
2018 May 04
2
How to constraint instructions reordering from patterns?
Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into
2018 May 04
0
How to constraint instructions reordering from patterns?
...@x3> 0, undef:i16 > >   t26: f32,ch = load<Volatile LD4[@x4](tbaa=<0x3dbe418>)> t25:1, > GlobalAddress:i16<float* @x4> 0, undef:i16 > >   t27: i16 = GlobalAddress<float (float, float, float, float)* > @fdivfaddfmul_a> 0 > >   t29: ch,glue = callseq_start t26:1, TargetConstant:i16<4> > >   t31: ch,glue = CLPISD::COPY_TO_CALLEE_A t29, t23, > FrameIndex:i16<0>, > t29:1 > >   t33: ch,glue = CLPISD::COPY_TO_CALLEE_A t31, t24, > FrameIndex:i16<1>, > t31:1 > >   t35: ch,glue = CLPISD::COPY_TO_C...
2009 Dec 09
2
[LLVMdev] PR 5723
On Tuesday 08 December 2009 15:53, Anton Korobeynikov wrote: > Hello, David > > > For X86 CALLSEQ_START gets selected to ADJCALLSTACKDOWN or > > ADJCALLSTACKDOWN64 in this case.  So is CALLSEQ_START expected > > to appear only once (at the top of the function)?  The comments > > are rather confusing.  It seems like CALLSEQ_START is supposed > > to appear before every cal...