search for: callpcrel32

...(); MachineBasicBlock * MBB = MF.CreateMachineBasicBlock(LLVM_BB); // create a MBB MBB->setNumber(19880616); // set the number of MBB to be 19880616 which is used as an ID Pred->addSuccessor(MBB); const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); DebugLoc dl; // CALLpcrel32 abort BuildMI(MBB,dl,TII->get(X86::CALLpcrel32)).addExternalSymbol("abort"); // JNE_4 error_label BuildMI(MBB,dl,TII->get(X86::JNE_4)).addExternalSymbol("error_label"); // MOV32ri %eax, 0 BuildMI(MBB,dl,TII->get(X86::MOV32ri),X86::EAX).addImm(0); // CA...

...bugInt is called first with @foo, then @foo+4, and the stores seem to be going to the right addresses as well: @foo and @foo+4! BB#0: derived from LLVM BB %entry PUSHi32 <ga:@foo>, %ESP<imp-def>, %ESP<imp-use> CFI_INSTRUCTION <call frame instruction> CALLpcrel32 <ga:@debugPointer>, <regmask %BH %BL %BP %BPL %BX %DI %DIL %EBP %EBX %EDI %ESI %SI %SIL>, %ESP<imp-use>, %ESP<imp-def>, %EAX<imp-def,dead>, %EDX<imp-def,dead> %ESP<def,tied1> = ADD32ri8 %ESP<tied0>, 4, %EFLAGS<imp-def,dead> CFI_I...

...e stores seem to be going to the right addresses as well: @foo and >> @foo+4! >> >> BB#0: derived from LLVM BB %entry >> PUSHi32 <ga:@foo>, %ESP<imp-def>, %ESP<imp-use> >> CFI_INSTRUCTION <call frame instruction> >> CALLpcrel32 <ga:@debugPointer>, <regmask %BH %BL %BP %BPL %BX >> %DI %DIL %EBP %EBX %EDI %ESI %SI %SIL>, %ESP<imp-use>, %ESP<imp-def>, >> %EAX<imp-def,dead>, %EDX<imp-def,dead> >> %ESP<def,tied1> = ADD32ri8 %ESP<tied0>, 4, %EFLAGS<imp...

Emitting calls to these functions (written in an .ll file linked in) works fine, and does the right thing. %Any = type { i8*, i32 } define dllexport void @setGlobal(%Any* %ptr, %Any %value) { store %Any %value, %Any* %ptr ret void } define dllexport %Any @getGlobal(%Any* %ptr) { %val = load %Any, %Any* %ptr ret %Any %val } Trying to replace the setGlobal call with what should be

...as well: >>>> @foo and @foo+4! >>>> >>>> BB#0: derived from LLVM BB %entry >>>> PUSHi32 <ga:@foo>, %ESP<imp-def>, %ESP<imp-use> >>>> CFI_INSTRUCTION <call frame instruction> >>>> CALLpcrel32 <ga:@debugPointer>, <regmask %BH %BL %BP %BPL %BX >>>> %DI %DIL %EBP %EBX %EDI %ESI %SI %SIL>, %ESP<imp-use>, %ESP<imp-def>, >>>> %EAX<imp-def,dead>, %EDX<imp-def,dead> >>>> %ESP<def,tied1> = ADD32ri8 %ESP<tied...

...// >> create a MBB >> MBB->setNumber(19880616); // set the number of MBB to be 19880616 >> which is used as an ID >> >> Pred->addSuccessor(MBB); >> const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); >> DebugLoc dl; >> // CALLpcrel32 abort >> BuildMI(MBB,dl,TII->get(X86::CALLpcrel32)).addExternalSymbol("abort"); >> // JNE_4 error_label >> BuildMI(MBB,dl,TII->get(X86::JNE_4)).addExternalSymbol("error_label"); >> // MOV32ri %eax, 0 >> BuildMI(MBB,dl,TII->ge...

...+4! >>>>>> >>>>>> BB#0: derived from LLVM BB %entry >>>>>> PUSHi32 <ga:@foo>, %ESP<imp-def>, %ESP<imp-use> >>>>>> CFI_INSTRUCTION <call frame instruction> >>>>>> CALLpcrel32 <ga:@debugPointer>, <regmask %BH %BL %BP %BPL >>>>>> %BX %DI %DIL %EBP %EBX %EDI %ESI %SI %SIL>, %ESP<imp-use>, %ESP<imp-def>, >>>>>> %EAX<imp-def,dead>, %EDX<imp-def,dead> >>>>>> %ESP<def,tied1>...

...g1025, 1, %NOREG, 0 %reg1027 = MOVSX32rm8 %reg1025, 1, %NOREG, 1 ADJCALLSTACKDOWN 8 %reg1028 = ADD32rr %reg1026, %reg1027 %reg1029 = IMUL32rr %reg1028, %reg1027 MOV32mr %ESP, 1, %NOREG, 4, %reg1029 MOV32mi %ESP, 1, %NOREG, 0, <ga:.str_1> CALLpcrel32 <ga:printf> ADJCALLSTACKUP 8, 0 %reg1030 = MOV32rr %EAX %reg1031 = IMPLICIT_DEF_GR32 %EAX = MOV32rr %reg1031 RET My allocator produces this mapping: FNSTCW16m := MOV8mi := FLDCW16m := MOV32rm EAX :...

...am trying to implement 'demultiplex' instruction as follows: demultiplex <multiplexid,choose,branch0id,branch1id,…,otherwisebranchid> In this case, the number of branch#id is not definite. It can be 1, 2, 3...or any number. My question was about this. I am still not sure how to use CALLpcrel32 you mentioned for this. Thank you very much. Seung Jae Lee

...m %EBP, 1, %NOREG, -4 %ESP = MOV32rr %EBP %EBP = POP32r RET codeRepl (0xa5f4148, LLVM BB @0xa5ce310, ID#82): Predecessors according to CFG: 0xa60ca80 %EDI = INC32r %EDI %EAX = MOV32rm %EBP, 1, %NOREG, -268 MOV32mr %EAX, 1, %NOREG, 0, %EDI CALLpcrel32 <ga:test3_trueBlock_trueBlock.ret.exitStub_newFuncRoot.ce_trueBlock.ret.exitStub.ret.exitStub.ret.exitStub.ret7> %EAX = MOV32rm %EBP, 1, %NOREG, -268 %ESI = MOV32rm %EAX, 1, %NOREG, 0 %ESP = SUB32ri %ESP, 8 MOV32mr %ESP, 1, %NOREG, 4, %ESI MOV32mi %ESP,...

...# Machine code for function main: Post SSA Frame Objects: fi#0: size=1024, align=4, at location [SP+4] fi#1: size=1024, align=4, at location [SP+4] BB#0: derived from LLVM BB %entry ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> CALLpcrel32 <ga:@bar>, <regmask>, %ESP<imp-use>, %ESP<imp-def> ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> RET # End machine code for function main. before replace frame indices # Machine code for function main: Post...

...n main: Post SSA > Frame Objects: > fi#0: size=1024, align=4, at location [SP+4] > fi#1: size=1024, align=4, at location [SP+4] > > BB#0: derived from LLVM BB %entry > ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> > CALLpcrel32 <ga:@bar>, <regmask>, %ESP<imp-use>, %ESP<imp-def> > ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> > RET > > # End machine code for function main. > > before replace frame indices > # Machine...

...cts: >> fi#0: size=1024, align=4, at location [SP+4] >> fi#1: size=1024, align=4, at location [SP+4] >> >> BB#0: derived from LLVM BB %entry >> ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, >> %ESP<imp-use> >> CALLpcrel32 <ga:@bar>, <regmask>, %ESP<imp-use>, %ESP<imp-def> >> ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, >> %ESP<imp-use> >> RET >> >> # End machine code for function main. >> >> before repla...

...%ESP = MOV32rm %EBP, 1, %NOREG, -268 %ESI = MOV32rm %EBP, 1, %NOREG, -224 %ESI = ADD32ri8 %ESI, 16 MOV32mi %ESI, 1, %NOREG, 0, 0 MOV32mi %ESI, 1, %NOREG, 4, 1073741824 MOV32mi %ESP, 1, %NOREG, 12, 1079574528 MOV32mi %ESP, 1, %NOREG, 8, 0 CALLpcrel32 <es:fmod> %ESP = ADD32ri8 %ESP, 16 FSTP64m %EBP, 1, %NOREG, -160 %EAX = MOV32rm %EBP, 1, %NOREG, -224 %EAX = ADD32ri8 %EAX, 24 %XMM0 = MOVSDrm %EBP, 1, %NOREG, -160 MOVSDmr %EBP, 1, %NOREG, -232, %XMM0 MOVSDmr %EAX, 1, %NOREG, 0, %XMM0...

CallFrameSetupOpcode is a pseudo opcode like X86::ADJCALLSTACKDOWN64. That means when the code is expected to be called before the pseudo instructions are eliminated. I don't know why it's not the case for you. A quick look at PEI code indicates the pseudo's should not have been removed at the time when replaceFrameIndices are run. Evan On Sep 25, 2013, at 8:57 AM, Krzysztof

...0, %reg0* * ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>* * %ECX<def> = MOV32rr %ESP* * MOV32mr %ECX, 1, %reg0, 4, %reg0, %EAX<kill>; mem:ST4[Stack+4]* * MOV32mi %ECX<kill>, 1, %reg0, 0, %reg0, <ga:@.str>; mem:ST4[Stack]* * CALLpcrel32 <ga:@printf>, %EAX<imp-def>, %ECX<imp-def,dead>, %ESP<imp-use>, ...* * ADJCALLSTACKUP32 8, 0, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>* * MOV32mi <fi#1>, 1, %reg0, 0, %reg0, 0* * %ECX<def> = MOV32rm <fi#1>, 1, %reg0, 0, %re...

Hello. I am making a LLVM backend for a new architecture XCC. During implementation of instructions for XCC, I found that there are instructions need more than 3 operands in the target language manual. I could implement insructions need 1, 2 or 3 operands thanks to the examples in the LLVM backends already offered by you guys. But, I am not sure about those kind of instructions needs many number

Hi All, I'm dealing with a problem where the spill/restore instructions inserted during scavenging span an adjustment of the SP/FP register. The result is that despite the base register (SP/FP) being changed between the spill and the restore, both store and load use the same immediate offset. I see code in the PEI (replaceFrameIndices) that is supposed to track the SP/FP adjustment:

...02<def> = COPY %ESP; GR32:%vreg202 MOV32mr %vreg202, 1, %noreg, 8, %noreg, %vreg19; mem:ST4[%118+8] GR32:%vreg202,%vreg19 MOV32mr %vreg202, 1, %noreg, 4, %noreg, %vreg18; mem:ST4[%118+4] GR32:%vreg202,%vreg18 MOV32mr %vreg202, 1, %noreg, 0, %noreg, %vreg0; mem:ST4[%118] GR32:%vreg202,%vreg0 CALLpcrel32 <es:sin>, %EAX<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>, ... ; line end-1 ADJCALLSTACKUP32 8, 0, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line end --...

...0 PUSH32rmm %vreg0, 1, %noreg, 8, %noreg, %ESP<imp-def>, %ESP<imp-use>; GR32:%vreg0 PUSH32rmm %vreg0, 1, %noreg, 4, %noreg, %ESP<imp-def>, %ESP<imp-use>; GR32:%vreg0 PUSH32rmm %vreg0<kill>, 1, %noreg, 0, %noreg, %ESP<imp-def>, %ESP<imp-use>; GR32:%vreg0 CALLpcrel32 <ga:@foo>, <regmask>, %ESP<imp-use>, %ESP<imp-def> ADJCALLSTACKUP32 32, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> This, rightly, gets flagged by the verifier. My proposal is to add an additional parameter to ADJCALLSTACKDOWN to express the...