search for: calleesav

...2, [R7+ 8] ; 4-byte Folded Reload MOV.L R1, [R7+ 12] ; 4-byte Folded Reload I've isolated the epilogue and prologue away from the function (they don't make use of R1 or R2, Calling convention states R0-R3 are used as inputs to a function. R1-R4 are marked as calleesaved. From the above code I cannot see any reason why R1 & R2 are being spilled, I assume the fault lies in my tablegen definitions (relevant ones reproduced below) : let isCommutable=1 in { def ADD32rrr : M819Inst<(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),"ADD.L\t{$dst,$src1 + $src2}...

On 2007-10-05, at 13:56, Arnold Schwaighofer wrote: > On 5 Oct 2007, at 19:41, Evan Cheng wrote: > >> In theory, any function can be marked fastcc. But llvm-gcc c / c++ >> frontend does *not* mark any external functions fastcc. Also, the >> optimizer only changes the calling convention of internal >> functions to fastcc. > > well i hope llvm-gcc won't

...I tried to filter the functions which will be optimized by putting a constraints that it should have attribute NoUnwind but that does not help. Is it possible to disable CFI generation? 2) R8D is a 48 bit register but pushing and popping such register is not allowed and current implementation for CalleeSaved Register also uses either 64 bit or 32 bit version of X86 instruction according to target. So here I think it may be good to push/pop R8 for R8D (i.e I don't want to change current implementation which inserts MI for CSR) for that I need to find biggest register for which given register is al...

...> violate > the ABI for callee, or you're restricted to do tail call lowering only > for internal functions, making all stuff inpractical. . Only > call-clobbered registers can be used to store pointer to callee (I'd > suggest %ecx on x86/32, btw). > yes i cannot use the calleesaved registers for calling. i realized that. likely i did not express myself clearly. (sorry for that) it is not me who is loading the target address to the callee saved register but the register allocator decides to load the function pointer to esi because it assumes it is safe to do so. norma...

...ther violate the ABI for callee, or you're restricted to do tail call lowering only for internal functions, making all stuff inpractical. . Only call-clobbered registers can be used to store pointer to callee (I'd suggest %ecx on x86/32, btw). > Or do i have to insert code into PEI::saveCalleeSavedRegisters to > detect that there is a tail called function that uses a callee saved > register and move it to another (EAX). You shouldn't use call-saved registers at all. Only call-clobbered. It seems, that you can use the trick similar to eh_return lowering (that case is somehow sp...

...ast for testing, add the same DwarfRegNum as for R8). > > > 2) R8D is a 48 bit register Why do you say that? For one thing, it is in a register class GR32 and holds only 32-bit values. -Hal > but pushing and popping such register is > not allowed and current implementation for CalleeSaved Register also > uses either 64 bit or 32 bit version of X86 instruction according to > target. So here I think it may be good to push/pop R8 for R8D (i.e I > don't want to change current implementation which inserts MI for > CSR) for that I need to find biggest register for which...

On Sat, Jul 9, 2016 at 12:18 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Jul 8, 2016, at 11:41 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > On Fri, Jul 8, 2016 at 11:46 PM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On Jul 8, 2016, at 11:12 AM, vivek pandya <vivekvpandya at gmail.com> wrote:

...o filter the functions which will be optimized by putting a constraints that it should have attribute NoUnwind but that does not help. Is it possible to disable CFI generation? > > 2) R8D is a 48 bit register but pushing and popping such register is not allowed and current implementation for CalleeSaved Register also uses either 64 bit or 32 bit version of X86 instruction according to target. So here I think it may be good to push/pop R8 for R8D (i.e I don't want to change current implementation which inserts MI for CSR) for that I need to find biggest register for which given register is al...

...D is 32 bit value. To get this working changing CC for cold functions to "preserve_all" seems to be easy and safe way. Let me know your thought about this. -Vivek > > -Hal > > > but pushing and popping such register is > > not allowed and current implementation for CalleeSaved Register also > > uses either 64 bit or 32 bit version of X86 instruction according to > > target. So here I think it may be good to push/pop R8 for R8D (i.e I > > don't want to change current implementation which inserts MI for > > CSR) for that I need to find biggest...

..."preserve_all" seems to be easy > and safe way. Let me know your thought about this. Sounds like a reasonable thing to try. -Hal > -Vivek > > -Hal > > > > but pushing and popping such register is > > > > not allowed and current implementation for CalleeSaved Register > > > also > > > > uses either 64 bit or 32 bit version of X86 instruction according > > > to > > > > target. So here I think it may be good to push/pop R8 for R8D > > > (i.e > > > I > > > > don't want to chan...

...e, or you're restricted to do tail call lowering >> only >> for internal functions, making all stuff inpractical. . Only >> call-clobbered registers can be used to store pointer to callee (I'd >> suggest %ecx on x86/32, btw). >> > > yes i cannot use the calleesaved registers for calling. i realized > that. likely i did not express myself clearly. (sorry for that) > it is not me who is loading the target address to the callee saved > register but the register allocator > decides to load the function pointer to esi because it assumes it is > s...

...;preserve_all" seems to be easy and safe way. Let me know your thought about this. > Sounds like a reasonable thing to try. > > -Hal > > > -Vivek > > -Hal > > > but pushing and popping such register is > > not allowed and current implementation for CalleeSaved Register also > > uses either 64 bit or 32 bit version of X86 instruction according to > > target. So here I think it may be good to push/pop R8 for R8D (i.e I > > don't want to change current implementation which inserts MI for > > CSR) for that I need to find biggest...

...easonable thing to try. >>> >>> -Hal >>> >>> >>> -Vivek >>> >>>> >>>> -Hal >>>> >>>> > but pushing and popping such register is >>>> > not allowed and current implementation for CalleeSaved Register also >>>> > uses either 64 bit or 32 bit version of X86 instruction according to >>>> > target. So here I think it may be good to push/pop R8 for R8D (i.e I >>>> > don't want to change current implementation which inserts MI for >>&g...