search for: calleecc

...le for + // tailcall elimination + virtual bool IsEligibleForTailCallElimination(SelectionDAG& DAG, + bool IsNextInstRet, + SDOperand Callee, + unsigned CalleeCC) const { + return false; + } + I am not too keen on "isNextInstRet". We should never use instruction ordering before scheduling to determine whether it's possible to perform an optimization. IsEligibleForTailCallElimination() should determine the feasibility on its own, n...

The patch is against revision 42247. -------------- next part -------------- A non-text attachment was scrubbed... Name: tailcall-src.patch Type: application/octet-stream Size: 62639 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070923/4770302f/attachment.obj>

...prevents tailcall optimization when both caller and callee have ccc, even when it is optimized without an option -tailcallopt. Is it intended or misoptimized? In X86ISelLowering.cpp:X86TargetLowering::IsEligibleForTailCallOptimization(): if (GuaranteedTailCallOpt) { if (IsTailCallConvention(CalleeCC) && CCMatch) return true; return false; } I know -tailcallopt changes calling conversion of fastcc to callee-pop. ps. I am tweaking tailcallopt on Win64. ...Takumi

...l elimination > + virtual bool IsEligibleForTailCallElimination(SelectionDAG& DAG, > + bool IsNextInstRet, > + SDOperand Callee, > + unsigned CalleeCC) > const { > + return false; > + } > + > > I am not too keen on "isNextInstRet". We should never use instruction > ordering before scheduling to determine whether it's possible to > perform an optimization. IsEligibleForTailCallElimination() should > det...

...t;> + virtual bool IsEligibleForTailCallElimination(SelectionDAG& DAG, >> + bool IsNextInstRet, >> + SDOperand Callee, >> + unsigned CalleeCC) >> const { >> + return false; >> + } >> + >> >> I am not too keen on "isNextInstRet". We should never use instruction >> ordering before scheduling to determine whether it's possible to >> perform an optimization. IsEligibleForTailC...

...al bool IsEligibleForTailCallElimination(SelectionDAG& DAG, > >> + bool IsNextInstRet, > >> + SDOperand Callee, > >> + unsigned CalleeCC) > >> const { > >> + return false; > >> + } > >> + > >> > >> I am not too keen on "isNextInstRet". We should never use instruction > >> ordering before scheduling to determine whether it's possible to > >> per...

...I don't understand your question. What do you mean by both caller and callee have ccc? Evan > Is it intended or misoptimized? > > In X86ISelLowering.cpp:X86TargetLowering::IsEligibleForTailCallOptimization(): > > if (GuaranteedTailCallOpt) { > if (IsTailCallConvention(CalleeCC) && CCMatch) > return true; > return false; > } > > I know -tailcallopt changes calling conversion of fastcc to callee-pop. > > ps. I am tweaking tailcallopt on Win64. > > ...Takumi > _______________________________________________ > LLVM Develop...

...whether the next instruction following the call is a return +// A function is eligable if caller/callee calling conventions match and the +// function CALL is immediatly followed by a RET +bool X86TargetLowering::IsEligibleForTailCallElimination(SDOperand Call, SelectionDAG& DAG, unsigned CalleeCC, SDOperand Callee) { + bool IsEligible = false; + SDNode * CallNode = Call.Val; ... +SDOperand X86TargetLowering::LowerX86_32FastCCCallTo(SDOperand Op, + SelectionDAG &DAG, + unsigned CC)...

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

...lElimination(SelectionDAG& DAG, >>>> + bool >>>> IsNextInstRet, >>>> + SDOperand Callee, >>>> + unsigned CalleeCC) >>>> const { >>>> + return false; >>>> + } >>>> + >>>> >>>> I am not too keen on "isNextInstRet". We should never use >>>> instruction >>>> ordering before scheduling to determine whethe...

...tion following the call is a > return > +// A function is eligable if caller/callee calling conventions match > and the > +// function CALL is immediatly followed by a RET > +bool X86TargetLowering::IsEligibleForTailCallElimination(SDOperand > Call, SelectionDAG& DAG, unsigned CalleeCC, SDOperand Callee) { > + bool IsEligible = false; > + SDNode * CallNode = Call.Val; > ... > > +SDOperand X86TargetLowering::LowerX86_32FastCCCallTo(SDOperand Op, > + SelectionDAG > &DAG, > +...

...The callee has to preserve all registers the caller needs to preserve. const X86RegisterInfo *TRI = Subtarget.getRegisterInfo(); const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC); if (!CCMatch) { const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC); if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) return false; } which usually checks that this is fine. Maybe that code looks at the regmask of the calling convention rather than the new regmask computed by IPRA? - Matthias On Aug 4, 2016, at 9:22 PM, vivek pandy...

...t;> preserve. >> const X86RegisterInfo *TRI = Subtarget.getRegisterInfo(); >> const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, >> CallerCC); >> if (!CCMatch) { >> const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, >> CalleeCC); >> if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) >> return false; >> } >> >> Thanks MatzeB for pointing this out. > >> which usually checks that this is fine. Maybe that code looks at the >> regmask of the calling conve...

----- Original Message ----- > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Quentin Colombet" > <qcolombet at apple.com>, "Mehdi Amini" <mehdi.amini at apple.com> > Sent: Friday, July 29, 2016 5:02:44 AM >