Displaying 20 results from an estimated 29 matches for "callconv".
2010 Mar 07
1
[LLVMdev] [PATCH] New calling convention for use by GHC
...by GHC, so really all of this could be changed so that it just returns
no callee saves regardless of ABI. Also, I assume EH = Exception
Handling? If so, no EHRet doesn't matter. The new patch takes this
approach.
>
>
> 4) In X86ISelLowering.cpp:
>
> - if (!Is64Bit&& CallConv != CallingConv::Fast&& ArgsAreStructReturn(Ins))
> + if (!Is64Bit&& CallConv != CallingConv::Fast&&
> + CallConv != CallingConv::GHC&& ArgsAreStructReturn(Ins))
>
> This should probably use !IsTailCallConvention(CallConv) instead of duplica...
2010 Mar 03
0
[LLVMdev] [PATCH] New calling convention for use by GHC
...CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
Seems like it could be simplified. Have you tested the Win64 support? It isn't clear why your patch needs to depend on the host ABI here. Also, does EHRet matter for your calling conv?
4) In X86ISelLowering.cpp:
- if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
+ if (!Is64Bit && CallConv != CallingConv::Fast &&
+ CallConv != CallingConv::GHC && ArgsAreStructReturn(Ins))
This should probably use !IsTailCallConvention(CallConv) instead of duplicating the two conve...
2010 Mar 03
2
[LLVMdev] [PATCH] New calling convention for use by GHC
...version of LLVM. If this patch isn't
something that you would want to include in LLVM can you suggest an
alternative way to do this that you would consider including?
Cheers,
David
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: llvm-ghc-callconv.patch
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100303/5ef61ebc/attachment.ksh>
2008 Dec 14
1
[LLVMdev] Tail calls from OCaml
How do you get a tail call using the OCaml's LLVM API?
--
Dr Jon Harrop, Flying Frog Consultancy Ltd.
http://www.ffconsultancy.com/?e
2011 Jan 21
1
[LLVMdev] why dummy asserting base/interface class virtual methods instead of pure virtual methods?
LLVM code base seems to be full of base/interface classes, which have
methods like
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,...
2012 May 25
0
[LLVMdev] Changes to TargetLowering::{LowerCallTo,LowerCall}
...DValue, 32> &OutVals = CLI.OutVals;
SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
SDValue Chain = CLI.Chain;
SDValue Callee = CLI.Callee;
bool &isTailCall = CLI.IsTailCall;
CallingConv::ID CallConv = CLI.CallConv;
bool doesNotRet = CLI.DoesNotReturn;
bool isVarArg = CLI.IsVarArg;
The CallLoweringInfo struct now contains all parameters that were originally available as parameters. The InVals vector was left as a parameter s...
2017 Apr 27
4
-msave-args backend support for x86_64
...ckRealignment(MF) ||
MFI.hasVarSizedObjects() ||
MFI.isFrameAddressTaken() || MFI.hasOpaqueSPAdjustment() ||
@@ -850,6 +851,25 @@
MI->getOperand(3).setIsDead();
}
+// FIXME: Get this from tablegen.
+static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
+ const X86Subtarget &Subtarget) {
+ assert(Subtarget.is64Bit());
+
+ if (Subtarget.isCallingConvWin64(CallConv)) {
+ static const MCPhysReg GPR64ArgRegsWin64[] = {
+ X86::RCX, X86::RDX, X86::R8, X86::R9
+ };
+ return makeArrayRef...
2015 Nov 25
2
need help for customized backend LowerFormalArguments
...ret i32 %1
}
I want the assembly looks like this:
move v0, p0
move v1, p1
add-int v10, v0, v1
return v10
So far, I have tried is to implement the LowerFormalArguments() like this:
SDValue FOOTargetLowering::LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(!isVarArg &&...
2011 Jun 16
3
[LLVMdev] ARM support status (GHC/ARM new calling convention)
...in llvm::CCState::AnalyzeCallOperands (this=0x8045c80,
Outs=@0x8046350,
Fn=0x88c7838 <ARM_AAPCS_GHC>) at CallingConvLower.cpp:126
#6 0x088cb08a in llvm::ARMTargetLowering::LowerCall (this=0x92b4c58, Chain=
{Node = 0x92d1b50, ResNo = 0}, Callee={Node = 0x92d1c60, ResNo = 0},
CallConv=llvm::CallingConv::GHC, isVarArg=false,
isTailCall=@0x804656b, Outs=@0x8046350,
OutVals=@0x8046230, Ins=@0x8045f30, dl={LineCol = 0, ScopeIdx = 0},
DAG=@0x92bdea8,
InVals=@0x80461f0) at ARMISelLowering.cpp:1209
#7 0x08aece19 in llvm::TargetLowering::LowerCallTo (this=0x92b4c58, Chain=...
2011 May 31
0
[LLVMdev] X86Subtarget.h could be beautified
Hi!
when reading X86Subtarget.h the methods seem a bit disordered, therefore
I would
propose to sort them new:
-getTargetTriple()
-cpu features (e.g. hasSSE1())
-os types (e.g. isTargetDarwin())
-object types (e.g. isTargetELF())
-callconv related functions (e.g. isTargetWin64(), consider renaming to
isCallConvWin64(),
getStackAlignment())
-pic functions
perhaps my problem of generating elf objects on windows can be easily
solved by creating
a new os type, just like mingw and cycwin, and patching X86Subtarget.h
accordingly
(of...
2016 May 11
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...e PowerPC backend, for example, looks like this:
>
> // Add a register mask operand representing the call-preserved registers.
> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
> const uint32_t *Mask =
> TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
> assert(Mask && "Missing call preserved mask for calling convention");
> Ops.push_back(DAG.getRegisterMask(Mask));
>
> but it can be more complicated. If you look for uses of 'getRegisterMask' in Target/*/*ISelLowering.cpp, you'll see what I mean. R...
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...e PowerPC backend, for example, looks like this:
>
> // Add a register mask operand representing the call-preserved registers.
> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
> const uint32_t *Mask =
> TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
> assert(Mask && "Missing call preserved mask for calling convention");
> Ops.push_back(DAG.getRegisterMask(Mask));
>
> but it can be more complicated. If you look for uses of 'getRegisterMask' in Target/*/*ISelLowering.cpp, you'll see what I mean. R...
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...he PowerPC backend, for example, looks like this:
>
> // Add a register mask operand representing the call-preserved registers.
> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
> const uint32_t *Mask =
> TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
> assert(Mask && "Missing call preserved mask for calling convention");
> Ops.push_back(DAG.getRegisterMask(Mask));
>
> but it can be more complicated. If you look for uses of 'getRegisterMask'
> in Target/*/*ISelLowering.cpp, you'll see what I mea...
2016 May 11
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...fo *TRI = Subtarget.getRegisterInfo();
> > > >
> > >
> >
>
> > > > > const uint32_t *Mask =
> > > >
> > >
> >
>
> > > > > TRI->getCallPreservedMask(DAG.getMachineFunction(),
> > > > > CallConv);
> > > >
> > >
> >
>
> > > > > assert(Mask && "Missing call preserved mask for calling
> > > > > convention");
> > > >
> > >
> >
>
> > > > > Ops.push_back(DAG.getRegis...
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...le, looks like this:
>>
>> // Add a register mask operand representing the call-preserved
>> registers.
>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>> const uint32_t *Mask =
>> TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
>> assert(Mask && "Missing call preserved mask for calling convention");
>> Ops.push_back(DAG.getRegisterMask(Mask));
>>
>> but it can be more complicated. If you look for uses of 'getRegisterMask'
>> in Target/*/*ISelLowering.cpp, you...
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya*
On Wed, May 11, 2016 at 10:02 AM, vivek pandya <vivekvpandya at gmail.com>
wrote:
>
>
> *Vivek Pandya*
>
>
> On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com>
> wrote:
>
>>
>> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>>
>>
>>
>>
2016 May 18
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...or example, looks like this:
>>
>> // Add a register mask operand representing the call-preserved registers.
>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>> const uint32_t *Mask =
>> TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
>> assert(Mask && "Missing call preserved mask for calling convention");
>> Ops.push_back(DAG.getRegisterMask(Mask));
>>
>> but it can be more complicated. If you look for uses of 'getRegisterMask' in Target/*/*ISelLowering.cpp, you'll se...
2016 May 24
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...;>>
>>> // Add a register mask operand representing the call-preserved
>>> registers.
>>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>>> const uint32_t *Mask =
>>> TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
>>> assert(Mask && "Missing call preserved mask for calling convention");
>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>
>>> but it can be more complicated. If you look for uses of
>>> 'getRegisterMask' in Target/*/*ISe...
2016 May 24
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...t; > > >
> > >
> >
>
> > > > > > const uint32_t *Mask =
> > > > >
> > > >
> > >
> >
>
> > > > > > TRI->getCallPreservedMask(DAG.getMachineFunction(),
> > > > > > CallConv);
> > > > >
> > > >
> > >
> >
>
> > > > > > assert(Mask && "Missing call preserved mask for calling
> > > > > > convention");
> > > > >
> > > >
> > >
> &...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...t;> // Add a register mask operand representing the call-preserved
>>>> registers.
>>>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>>>> const uint32_t *Mask =
>>>> TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
>>>> assert(Mask && "Missing call preserved mask for calling convention");
>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>
>>>> but it can be more complicated. If you look for uses of
>>>> 'getRegisterMask...