search for: call64pcrel32

...is the resulting code (it's a simple program with some 'if'): (null) BB#4 JMP_4 <BB#0> if.end BB#3 %RDI<def> = LEA64r %RIP, 1, %noreg, <ga:@.str2>, %noreg ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> %AL<def> = MOV8ri 0 CALL64pcrel32 <ga:@printf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use,kill>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> %ECX<def> = MOV32ri 25 MOV32mr <fi#8>, 1, %noreg, 0, %noreg, %EAX<k...

...erstanding of a "dead" register is a def that is never used. However, when I dump the MI after reg alloc on a simple program I see the following sequence: ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def %rsp, implicit-def %ssp ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead %eflags,...

...register is a def that is never used. However, > when I dump the MI after reg alloc on a simple program I see the > following sequence: > > ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead > %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp > CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx > %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d > %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def > %rsp, implicit-def %ssp > ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, impl...

...9;ve tried to find information but could not find any clear definition.) For example BranchFolder may do things like this (also see https://godbolt.org/z/iphFH4): # *** IR Dump Before Control Flow Optimizer ***: bb.0.entry: ... JCC_1 %bb.2, 5, implicit killed $eflags JMP_1 %bb.1 bb.1.s1: CALL64pcrel32 @bar, ... , implicit-def $rax MOV16mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $bx :: (store 2 into %ir.r) JMP_1 %bb.3 bb.2.s2: CALL64pcrel32 @bar, ... , implicit-def $rax MOV16mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $bx :: (store 2 into %ir.r2) bb.3.cond.end...

...ain> LEA64r %reg1025<d> %mreg(0) 1 %mreg(0) <ga:initialized$$$CFE_id_cc092431_main> 24 %RDI = MOV64rr %reg1025<kill> MOV64rr %mreg(78)<d> %reg1025 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp-def,dead>, %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp-def,dead>, %FP0<imp-def,dead>, %FP1&l...

In X86CodeGen.cpp, the following code appears in the handler used for CALL64pcrel32 instructions: // Assume undefined functions may be outside the Small codespace. bool NeedStub = (Is64BitMode && (TM.getCodeModel() == CodeModel::Large || TM.getSubtarget<X86Subtarget>().isTargetDarwin())) || Opcode == X...

On Jun 26, 2007, at 11:20 AM, David A. Greene wrote: > > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> > 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp- > def,dead>, > %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, > %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp- > def,dead>, > %FP0&l...

...g CMP64rm %R11, %noreg, 1, %noreg, 40, %GS, %EFLAGS<imp-def> JA_1 <BB#0>, %EFLAGS<imp-use> Successors according to CFG: BB#3 BB#0 BB#3: Predecessors according to CFG: BB#4 %R10<def> = MOV64ri 40040 %R11<def> = MOV64ri 32 CALL64pcrel32 <es:__morestack>, %RSP<imp-use> MORESTACK_RET Successors according to CFG: BB#0 BB#0: derived from LLVM BB %0 Predecessors according to CFG: BB#3 BB#4 %EAX<def> = MOV32ri 40040; flags: FrameSetup %RDX<def> = MOV64rr %RAX; flags: FrameSetup...

...g so quickly. > > On Tuesday 26 June 2007 14:11, Evan Cheng wrote: >> On Jun 26, 2007, at 11:20 AM, David A. Greene wrote: >>> 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> >>> MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> >>> 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp- >>> def,dead>, >>> %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, >>> %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp- >>...

..., thanks for responding so quickly. On Tuesday 26 June 2007 14:11, Evan Cheng wrote: > On Jun 26, 2007, at 11:20 AM, David A. Greene wrote: > > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> > > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> > > 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp- > > def,dead>, > > %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, > > %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp- > > def,dea...

On Jun 10, 2009, at 12:17 PM, Jeffrey Yasskin wrote: > In X86CodeGen.cpp, the following code appears in the handler used for > CALL64pcrel32 instructions: > > // Assume undefined functions may be outside the Small > codespace. > bool NeedStub = > (Is64BitMode && > (TM.getCodeModel() == CodeModel::Large || > TM.getSubtarget<X86Subtarget>().isTargetDarw...

I discovered recently that RegAllocFast spills all the registers before every function call. This is the root cause of one of our recursive functions that takes about 150 bytes of stack when built with gcc (same at -O0 and -O2, or 120 bytes at llc -O2) taking 960 bytes of stack when built by llc -O0. That's pretty bad for situations where you have small stacks, which is not uncommon for

...m LLVM BB %entry ADJCALLSTACKDOWN64 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %vreg2<def> = MOV32ri64 <ga:@str>; GR32:%vreg2 %vreg3<def> = SUBREG_TO_REG 0, %vreg2<kill>, 4; GR64:%vreg3 GR32:%vreg2 %RDI<def> = COPY %vreg3; GR64:%vreg3 CALL64pcrel32 <ga:@puts>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSP<imp-def>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %vreg4<def> = COPY %EAX; GR32:%vreg4 BURNSTACK %EFLAGS<imp-def,dead> %v...

...lt;imp-def>, %RSP<imp-use> %reg1030<def> = LEA64r %RIP, 1, %reg0, <ga:@.str> %reg1031<def> = MOV8r0 %EFLAGS<imp-def,dead> %RDI<def> = MOV64rr %reg1030 %ESI<def> = MOV32rr %reg1028 %EDX<def> = MOV32rr %reg1029 %AL<def> = MOV8rr %reg1031 CALL64pcrel32 <ga:@printf>, %RDI, %ESI, %EDX, %AL, %RAX<imp-def>, %RDX<imp-def>, %RSI<imp-def>, %RDI<imp-def>, %RSP<imp-use>, ... When finding a register for %reg1028, RAFast sees that it is later copied to %ESI. It is allocated %ESI and the copy disappears: %ESI<def>...

On Tue, Jul 28, 2015 at 6:34 PM, Reid Kleckner <rnk at google.com> wrote: > On Tue, Jul 28, 2015 at 2:25 AM, John Kåre Alsaker > <john.mailinglists at gmail.com> wrote: >> >> On Tue, Jul 28, 2015 at 12:44 AM, Reid Kleckner <rnk at google.com> wrote: >> > Yeah, the function attributes section of LangRef is a reasonable place >> > to >>

...def> = MOV64rr %reg1028<kill> 60 %XMM0<def> = FsMOVAPDrr %reg1027 68 %XMM1<def> = FsMOVAPDrr %reg1027 76 %XMM2<def> = FsMOVAPDrr %reg1027 84 %XMM3<def> = FsMOVAPDrr %reg1027<kill> 92 %AL<def> = MOV8rr %reg1026<kill> 100 CALL64pcrel32 <ga:printf>, %RDI<kill>, %XMM0<kill>, %XMM1<kill>, %XMM2<kill>, %XMM3<kill>, %AL<kill>, %RAX<imp-def>, %RCX<imp-def,dead>, %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, %R8<imp-def,dead>, %R9<imp-def,dead...

On Thu, Jun 11, 2009 at 12:54 PM, Evan Cheng<evan.cheng at apple.com> wrote: > > > > On Jun 10, 2009, at 12:17 PM, Jeffrey Yasskin wrote: > >> In X86CodeGen.cpp, the following code appears in the handler used for >> CALL64pcrel32 instructions: >> >>       // Assume undefined functions may be outside the Small codespace. >>       bool NeedStub = >>         (Is64BitMode && >>             (TM.getCodeModel() == CodeModel::Large || >>              TM.getSubtarget<X86Subtarget>()....

I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

...kill> > 60 %XMM0<def> = FsMOVAPDrr %reg1027 > 68 %XMM1<def> = FsMOVAPDrr %reg1027 > 76 %XMM2<def> = FsMOVAPDrr %reg1027 > 84 %XMM3<def> = FsMOVAPDrr %reg1027<kill> > 92 %AL<def> = MOV8rr %reg1026<kill> > 100 CALL64pcrel32 <ga:printf>, %RDI<kill>, %XMM0<kill>, > %XMM1<kill>, %XMM2<kill>, %XMM3<kill>, %AL<kill>, %RAX<imp-def>, > %RCX<imp-def,dead>, %RDX<imp-def,dead>, %RSI<imp-def,dead>, > %RDI<imp-def,dead>, %R8<imp-def,dead>, %R9&...