search for: calculatecalleesavedregist

Hi, I am confused about the call to isPhyRegUsed in calculateCalleeSavedRegisters: if (Fn.getRegInfo().isPhysRegUsed(Reg)) { // If the reg is modified, save it! CSI.push_back(CalleeSavedInfo(Reg)); } It seems that isPhyRegUsed returns true if the register is read or written in the function. If this is right, why do we save a register if it is only read in the functio...

...set = MaxOffset - Offset + saveAreaOffset;" line). Is there a reason why llvm doesn't keep around the offsets in the right order from very beginning, by pushing the CSRs in increasing order of FrameIdxs? [1]: in fact, the way X86FrameLowering's spillCalleeSavedRegisters and PEI's calculateCalleeSavedRegisters are set up, I don't see a reason why the FrameIdxs and the generated push instructions have any relation at all. It seems that the code relies on MFI->CreateStackObject returning sequential integers. Thanks! -- Sanjoy

...aved and 8 caller-saved. The default stack size is 4 bytes. The target implements dynamic stack realign to make sure the stack will always be aligned correctly when necessary. Yet I am still getting unaligned load/store when running this test case: http://pastie.org/8490604 The problem is in PEI::calculateCalleeSavedRegisters: // We may not be able to satisfy the desired alignment specification of // the TargetRegisterClass if the stack alignment is smaller. Use the // min. Align = std::min(Align, StackAlign); FrameIdx = MFI->CreateStackObject(RC->getSize(), Align, true); This wi...

Hi (Adding the list back in). On 1 August 2013 08:44, Liu Xin <navy.xliu at gmail.com> wrote: > i know where to calculate CSRs. the additional stack space is calculated in > PEI::calculateCalleeSavedRegisters. the real instructions are inserted in > insertCSRSpillsAndRestores. > my point is why llvm code honor 'naked' but does not 'noreturn' for CSR. And to me it sounds like a good point, but it should probably be done carefully so that LLVM's internal data structures remai...

> That is irrelevant. The PEI code needs to know how much stack space is > required for each call to allocate and align the stack frame properly. It > gets this info from the ADJCALLSTACK instructions. I see. Looking at PEI::calculateCalleeSavedRegisters shows that the ADJCALLSTACK instructions is used to set up MaxCallFrameSize. Adding debug prints also show that in the example code the ADJCALLSTACK argument is 4. I believe that this is the correct argument for only a 32bit integer is passed on the stack. The problem is that MaxCallFrameSize i...

hi, list, i am making a llvm compiler for shader-like programs. as we known, shader programs are short and have less function calls. i found that i have to save/restore callee-saved register(CSR) in prolog and epilog. because I can violate ABI from driver(c code) and shader, i plan to append the attribute 'noreturn' to all shader functions. in PrologEpilogInserter.cpp, you can find that

...implemented as an argument to createIPRAPass() method. B. While running the register allocator for a node, make use of the RegMask from the child nodes to compute the registers available for this node. C. Immediately after the register allocator is run for the node, run calculateCalleeSavedRegisters() on that node and save that info. I think the current method already saves this info in MFI, so we do not have to do any extra work to save it for later use. D. Update the RegMask for the node so that its parents know what registers to use. 5. Since calculateCalleeSavedReg...

...dynamic stack realign to make sure the stack > > will always be aligned correctly when necessary. > > > > > > Yet I am still getting unaligned load/store when running this test > > case: http://pastie.org/8490604 > > > > > > The problem is in PEI::calculateCalleeSavedRegisters: > > > > > > > > // We may not be able to satisfy the desired alignment > > specification > > of > > // the TargetRegisterClass if the stack alignment is smaller. Use > > the > > // min. > > Align = std::min(Align, StackAlign); >...

Hi Jakob, On Thu, Oct 4, 2012 at 2:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Oct 4, 2012, at 2:27 PM, "Madhusudan C.S" <madhusudancs at gmail.com> > wrote: > > Basically, the PrologEpilogInsertion pass will add a bit mask to >> MachineModuleInfo describing which registers are clobbered by the function >> being compiled. Later,

...is 4 bytes. > The target implements dynamic stack realign to make sure the stack > will always be aligned correctly when necessary. > > > Yet I am still getting unaligned load/store when running this test > case: http://pastie.org/8490604 > > > The problem is in PEI::calculateCalleeSavedRegisters: > > > > // We may not be able to satisfy the desired alignment specification > of > // the TargetRegisterClass if the stack alignment is smaller. Use the > // min. > Align = std::min(Align, StackAlign); > FrameIdx = MFI->CreateStackObject(RC->getSize(), Align...

...solve this, it also seems to require to reversing the order of XMM/YMM registers within calling convention definitions in X86CallingConv.td, and to do other minor changes to account for these. >> [1]: in fact, the way X86FrameLowering's spillCalleeSavedRegisters and >> PEI's calculateCalleeSavedRegisters are set up, I don't see a reason >> why the FrameIdxs and the generated push instructions have any >> relation at all. It seems that the code relies on >> MFI->CreateStackObject returning sequential integers. >> >> Thanks! >> -- Sanjoy >> >&gt...

...ration out of TRI, perhaps into its own "component" is one architecture I am looking at. > When is shrink wrapping happening? Is it possible to do it after CSR > spills and restores are inserted but before FI are lowered into sp / > fp +/- offset? Shrink wrapping starts after calculateCalleeSavedRegisters(), which creates the list of CSRs used in the function. Shrink wrapping assigns MBB placements for spills and restores based on where they are used. calculateCalleeSavedRegisters() determines stack slots for the CSRs used in the function. I don't see an interaction between this and shrink wr...

...he stack > > > will always be aligned correctly when necessary. > > > > > > > > > Yet I am still getting unaligned load/store when running this test > > > case: http://pastie.org/8490604 > > > > > > > > > The problem is in PEI::calculateCalleeSavedRegisters: > > > > > > > > > > > > // We may not be able to satisfy the desired alignment > > > specification > > > of > > > // the TargetRegisterClass if the stack alignment is smaller. Use > > > the > > > // min. > >...

...> will always be aligned correctly when necessary. > > > > > > > > > Yet I am still getting unaligned load/store when running this > > > test > > > case: http://pastie.org/8490604 > > > > > > > > > The problem is in PEI::calculateCalleeSavedRegisters: > > > > > > > > > > > > // We may not be able to satisfy the desired alignment > > > specification > > > of > > > // the TargetRegisterClass if the stack alignment is smaller. Use > > > the > > > // min. > &g...

...targets at once. We can ask targets to opt in to take advantage of shrink wrapping. > > When is shrink wrapping happening? Is it possible to do it after CSR > spills and restores are inserted but before FI are lowered into sp / > fp +/- offset? > > Shrink wrapping starts after calculateCalleeSavedRegisters(), which > creates the list of CSRs used in the function. Shrink wrapping > assigns MBB placements for spills and restores based on where they > are used. calculateCalleeSavedRegisters() determines stack slots for > the CSRs used in the function. > I don't see an inter...

...atile and not callee-saved.) X86RegisterInfo::getCalleeSavedRegs() when called for a Win64 target does return an array of registers which includes X86::XMM6 through X86:XMM15. However, the prolog/epilog code does not seem to be able handle saving these registers correctly. Firstly, in PEI::CalculateCalleeSavedRegisters() in CodeGen/ PrologEpilogInserter.cpp, the call to Fn.getRegInfo().isPhysRegUsed(Reg) always seems to return true for the all of the XMM registers if the Function being emitted makes any function calls whatsoever, and so it tries to save all thecallee-saved XMM registers even when none...

...better to wait until calculateFrameObjectOffsets computes the exact stack size to make the decision and redo the stack size calculation only if the spill slot is needed. bool PEI::runOnMachineFunction(MachineFunction &Fn) { ... TFI->processFunctionBeforeCalleeSavedScan(Fn, RS); ... calculateCalleeSavedRegisters(Fn); ... calculateFrameObjectOffsets(Fn); ... if (target needs spill slot) { call setScavengingFrameIndex and reserve spill slot calculateFrameObjectOffsets(Fn); // redo calculation. } This seems to be simpler and more efficient since you don't need to write or run a func...

On Sat, 7 Oct 2006, [UTF-8] Rafael Esp?ndola wrote: >> This sounds like the ADJCALLSTACK DOWN/UP 'instructions' around the call >> aren't set right, or you have declared a SP offset. It doesn't look like >> the ARM backend does this, so this is probably the problem. > The ARM backend currently doesn't use a frame pointer. It uses the > same technique

On Feb 26, 2009, at 2:02 PM, John Mosby wrote: > Hello LLVMdev, > > I have been working with LLVM for just over a year now, mainly in > the area of compilation for HDLs like SystemVerilog and SystemC. > Most of this work dealt with translation to LLVM IR, representing > concurrent languages with LLVM and using LLVM analyses and transforms > for compiling onto proprietary

> This sounds like the ADJCALLSTACK DOWN/UP 'instructions' around the call > aren't set right, or you have declared a SP offset. It doesn't look like > the ARM backend does this, so this is probably the problem. The ARM backend currently doesn't use a frame pointer. It uses the same technique of the PPC backend to avoid add/subs around calls. In the PPC backend we