Displaying 6 results from an estimated 6 matches for "calc_p".
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calc_pi
2013 Nov 16
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...0400000) {
+ case 0x00400000:
+ return clk->read(clk, nv_clk_src_core) >> P;
+ break;
+ default:
+ return 500000 >> P;
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
+ return 0;
+}
+
+static u32
+calc_pll(struct nvaa_clock_priv *priv, u32 reg,
+ u32 clock, int *N, int *M, int *P)
+{
+ struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvbios_pll pll;
+ struct nouveau_clock *clk = &priv->base;
+ int ret;
+
+ ret = nvbios_pll_parse(bios, reg, &pll);
+ if (ret)
+ return 0;
+
+ pll....
2013 Nov 17
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...0400000) {
+ case 0x00400000:
+ return clk->read(clk, nv_clk_src_core) >> P;
+ break;
+ default:
+ return 500000 >> P;
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
+ return 0;
+}
+
+static u32
+calc_pll(struct nvaa_clock_priv *priv, u32 reg,
+ u32 clock, int *N, int *M, int *P)
+{
+ struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvbios_pll pll;
+ struct nouveau_clock *clk = &priv->base;
+ int ret;
+
+ ret = nvbios_pll_parse(bios, reg, &pll);
+ if (ret)
+ return 0;
+
+ pll....
2013 Nov 09
2
[PATCH] drm/nouveau/clk: Initial implementation for reclocking NVAA/NVAC
Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to
2013 Dec 06
2
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
...m/nouveau/core/subdev/clock/nvaa.c:525:1: error: redefinition of 'nvaa_clock_read'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:80:1: note: previous definition of 'nvaa_clock_read' was here
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:607:1: error: conflicting types for 'calc_pll'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:162:1: note: previous definition of 'calc_pll' was here
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:628:1: error: redefinition of 'calc_P'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:183:1: note: previous definition o...
2013 Dec 06
0
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
...core/subdev/clock/nvaa.c:525:1: error: redefinition of 'nvaa_clock_read'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:80:1: note: previous definition of 'nvaa_clock_read' was here
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:607:1: error: conflicting types for 'calc_pll'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:162:1: note: previous definition of 'calc_pll' was here
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:628:1: error: redefinition of 'calc_P'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:183:1: note: previo...
2013 Dec 06
2
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
Hello everyone,
the current git HEAD of Linus Torvalds tree breaks Nouveau on my Mac Mini
Model 2010. I get variation of the following kernel panic when booting.
(gateway) [~] nc -u -l -p 6666
[ 3.796018] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 3.796100] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 3.796304] ata1.00: ATA-7: INTEL SSDSA2M160G2GC, 2CV102HA, max