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...af20fba..f4a2eb9 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > { > int ret; > > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) You don't want to do it also for tt_wc ? > + ttm_dma_tt_cache_sync_for_device((struct ttm_dma_tt *)nvbo->bo.ttm, > + &nouveau_bdev(nvbo->bo.ttm->bdev)->dev->pdev->dev); > + > ret = ttm_bo_validate(&nvbo->bo, &nvbo->placemen...

..._SYNC > +void > +nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) > +{ > + struct nouveau_device *device; > + struct ttm_tt *ttm = nvbo->bo.ttm; > + > + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); > + > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) > + ttm_dma_tt_cache_sync_for_cpu((struct ttm_dma_tt *)nvbo->bo.ttm, > + nv_device_base(device)); Can we be certain at this point that the struct ttm_tt is in fact a struct ttm_dma_tt? > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/no...

...-- a/drivers/gpu/drm/nouveau/nouveau_bo.c > > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > > @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > > { > > int ret; > > > > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) > > You don't want to do it also for tt_wc ? > No the point of using writecombined memory for BOs is to explicitly avoid the need for this cache sync. An uncached MMIO read from the device should already flush out all writecombining buffers and this read is always ha...

...gpu/drm/nouveau/nouveau_bo.c index af20fba..f4a2eb9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, { int ret; + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) + ttm_dma_tt_cache_sync_for_device((struct ttm_dma_tt *)nvbo->bo.ttm, + &nouveau_bdev(nvbo->bo.ttm->bdev)->dev->pdev->dev); + ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible, no_wait_gpu); if (ret) diff --git a/d...

...a/drm/nouveau_bo.c b/drm/nouveau_bo.c index 686fbd62381e..038d7e30c305 100644 --- a/drm/nouveau_bo.c +++ b/drm/nouveau_bo.c @@ -1573,8 +1573,10 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) * so use the DMA API for them. */ if (!nv_device_is_cpu_coherent(device) && - ttm->caching_state == tt_uncached) + ttm->caching_state == tt_uncached) { ttm_dma_unpopulate(ttm_dma, dev->dev); + return; + } #if __OS_HAS_AGP if (drm->agp.stat == ENABLED) { -- 2.1.3

...) return 0; } +#ifdef NOUVEAU_NEED_CACHE_SYNC +void +nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) +{ + struct nouveau_device *device; + struct ttm_tt *ttm = nvbo->bo.ttm; + + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); + + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) + ttm_dma_tt_cache_sync_for_cpu((struct ttm_dma_tt *)nvbo->bo.ttm, + nv_device_base(device)); +} + +void +nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) +{ + struct ttm_tt *ttm = nvbo->bo.ttm; + + if (ttm && ttm->caching_state == tt_cached) { + str...

...;ttm.num_pages, > + sizeof(*ttm->dma_address), > + GFP_KERNEL | __GFP_ZERO); > + if (!ttm->dma_address) > + return -ENOMEM; > + return 0; > +} > + > #ifdef CONFIG_X86 > static inline int ttm_tt_set_page_caching(struct page *p, > enum ttm_caching_state c_old, > @@ -227,8 +237,8 @@ void ttm_tt_destroy(struct ttm_tt *ttm) > ttm->func->destroy(ttm); > } > > -int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev, > - unsigned long size, uint32_t page_flags) > +void ttm_tt_init_fields(struct ttm_tt *ttm,...

...ouveau_ttm_tt_populate(struct ttm_tt *ttm) dev = drm->dev; pdev = device->dev; - /* - * Objects matching this condition have been marked as force_coherent, - * so use the DMA API for them. - */ - if (!nvxx_device(&drm->device)->func->cpu_coherent && - ttm->caching_state == tt_uncached) - return ttm_dma_populate(ttm_dma, dev->dev); - #if IS_ENABLED(CONFIG_AGP) if (drm->agp.bridge) { return ttm_agp_tt_populate(ttm); @@ -1557,16 +1516,6 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) dev = drm->dev; pdev = device->dev; - /* - * Objects m...

This is the first set of patches to make Nouveau work on Tegra. Those are only the obvious correctness fixes, a lot of optimization work remains to be done, but at least it's enough to get accel working and let the machine survive a piglit run. A new BO flag is introduced to allow userspace to hint the kernel about possible optimizations. Lucas Stach (6): drm/ttm: recognize ARM arch in

This small series introduces TTM helper functions as well as Nouveau hooks that are needed to ensure buffer coherency on ARM. Most of this series is a forward-port of some patches Lucas Stach sent last year and that are also needed for Nouveau GK20A support: http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html Another patch takes care of flushing the CPU write-buffer when

For this v2 I have fixed the patches that are non-controversial (all Lucas' :)) and am resubmitting them in the hope that they will get merged. This will just leave the issue of Nouveau system-memory buffers mapping to be solved. This issue is quite complex, so let me summarize the situation and the data I have at hand. ARM caching is like a quantum world where Murphy's law constantly

It has been a couple of months since v4 - apologies for this. v4 has not received many comments, but this version addresses them and makes a new attempt at pushing the critical bit for GK20A and Nouveau on ARM in general. As a reminder, this series addresses the memory coherency issue that we are seeing on ARM platforms. Contrary to x86 which invalidates the PCI caches whenever a write is made by

...             GFP_KERNEL | __GFP_ZERO); >> +    if (!ttm->dma_address) >> +        return -ENOMEM; >> +    return 0; >> +} >> + >>   #ifdef CONFIG_X86 >>   static inline int ttm_tt_set_page_caching(struct page *p, >>                         enum ttm_caching_state c_old, >> @@ -227,8 +237,8 @@ void ttm_tt_destroy(struct ttm_tt *ttm) >>       ttm->func->destroy(ttm); >>   } >>   -int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev, >> -        unsigned long size, uint32_t page_flags) >> +void ttm_tt_init...

Another revision of this patchset critical for GK20A to operate. Previous attempts were exclusively using either TTM's regular page allocator or the DMA API one. Both have their advantages and drawbacks: the page allocator is fast but requires explicit synchronization on non-coherent architectures, whereas the DMA allocator always returns coherent memory, but is also slower, creates a