Displaying 1 result from an estimated 1 matches for "cacheptrs".
2009 Mar 31
1
[PATCH 1/1] CORE/cache: add cache priority parameter
...@@ getcachesector:
; Update LRU, then compute buffer address
TRACER 'H'
+ ; Skip LRU update if DX == 0
+ and dx,dx ; Set ZF
+ jz .hit_no_lru
+
; Remove from current position in the list
mov bx,[si+cptr.prev]
mov di,[si+cptr.next]
@@ -95,6 +101,8 @@ getcachesector:
mov [CachePtrs+cptr.prev],si
mov word [si+cptr.next],CachePtrs
+.hit_no_lru:
+ and ax,ax ; Clear ZF
sub si,CachePtrs+cptr_size
shl si,SECTOR_SHIFT-cptr_size_lg2 ; Buffer address
diff --git a/core/extlinux.asm b/core/extlinux.asm
index 9684c8a..59d460d 100644
--- a/core/extlinux.asm
+++ b/core/extlinux...