Displaying 5 results from an estimated 5 matches for "cacheadd".
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2018 Mar 19
4
Generating a custom opcode from an LLVM intrinsic
...at line 358 of llvm/lib/Target/X86/X86InstrFormats.td, which
helps a lot.
Let's assume I want to produce opcode 0x16 (which I'm using because it
doesn't seem to be implemented in gem5 otherwise, and would simply produce
a warning). Then my guess is that I should use something like:
def CACHEADD : I<0x16, FORMAT, (outs), (ins),
ASM, [(int_cache_add)]>, PD;
where FORMAT comes from
http://legup.eecg.utoronto.ca/doxygen/namespacellvm_1_1X86II.html
and ASM = ???
and i deleted IIC_SSE_PREFETCH (because I'm not sure what this flag
indicates, but I assume it's n...
2018 Mar 19
0
Generating a custom opcode from an LLVM intrinsic
...t/X86/X86InstrFormats.td, which
> helps a lot.
>
> Let's assume I want to produce opcode 0x16 (which I'm using because it
> doesn't seem to be implemented in gem5 otherwise, and would simply produce
> a warning). Then my guess is that I should use something like:
> def CACHEADD : I<0x16, FORMAT, (outs), (ins),
> ASM, [(int_cache_add)]>, PD;
>
> where FORMAT comes from http://legup.eecg.utoronto.ca/doxygen/
> namespacellvm_1_1X86II.html
> and ASM = ???
> and i deleted IIC_SSE_PREFETCH (because I'm not sure what this flag
>...
2018 Mar 20
1
Generating a custom opcode from an LLVM intrinsic
..., which
>> helps a lot.
>>
>> Let's assume I want to produce opcode 0x16 (which I'm using because it
>> doesn't seem to be implemented in gem5 otherwise, and would simply produce
>> a warning). Then my guess is that I should use something like:
>> def CACHEADD : I<0x16, FORMAT, (outs), (ins),
>> ASM, [(int_cache_add)]>, PD;
>>
>> where FORMAT comes from http://legup.eecg.utoront
>> o.ca/doxygen/namespacellvm_1_1X86II.html
>> and ASM = ???
>> and i deleted IIC_SSE_PREFETCH (because I'm not...
2018 Mar 18
0
Generating a custom opcode from an LLVM intrinsic
Here's a couple examples for mapping an intrinsic to an X86 instruction
from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
find others.
let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
2018 Mar 18
2
Generating a custom opcode from an LLVM intrinsic
Hello all. LLVM newbie here. If anything seems glaringly wrong with my use
of LLVM, that's probably why.
Here's what I'm trying to do. I have modified the gem5 simulator to accept
a "new" x86 instruction. I've done this by just reserving the opcode in
gem5's ISA specification, just as all other instructions are specified.
I'm trying to get an LLVM backend to