search for: cacheably

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On Thu, Feb 09, 2017 at 08:17:16PM +0200, Michael S. Tsirkin wrote: > > On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > > > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > > > I am inclined to say, for 4.10 let's revert > > > >

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On Thu, Feb 09, 2017 at 08:17:16PM +0200, Michael S. Tsirkin wrote: > > On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > > > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > > > I am inclined to say, for 4.10 let's revert > > > >

On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > I am inclined to say, for 4.10 let's revert > > c7070619f3408d9a0dffbed9149e6f00479cf43b since what it fixes is not a > > regression in 4.10. > > No complaints there, as long as we can keep working to fix this for 4.11 > and

On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > I am inclined to say, for 4.10 let's revert > > c7070619f3408d9a0dffbed9149e6f00479cf43b since what it fixes is not a > > regression in 4.10. > > No complaints there, as long as we can keep working to fix this for 4.11 > and

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On ARM (and other archs such as > Power), having a mismatch between a cacheable and a non-cacheable mapping > can result in a loss of coherency between the two (for example, if the > non-cacheable gues accesses bypass the cache, but the cacheable host > accesses allocate in the cache). I guess it's an optimization

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On ARM (and other archs such as > Power), having a mismatch between a cacheable and a non-cacheable mapping > can result in a loss of coherency between the two (for example, if the > non-cacheable gues accesses bypass the cache, but the cacheable host > accesses allocate in the cache). I guess it's an optimization

Hi guys, I''ve fixed a pretty annoying bug in Action caching that is detailed here: https://rails.lighthouseapp.com/projects/8994/tickets/6480-action-cache-filter-code-incorrectly-renders-nil-response-body-if-response-is-non-cacheable Would appreciate testers or a direct commit if it checks out :) Cheers, Chu Yeow -- You received this message because you are subscribed to the Google

On Thu, Feb 09, 2017 at 08:17:16PM +0200, Michael S. Tsirkin wrote: > On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > > I am inclined to say, for 4.10 let's revert > > > c7070619f3408d9a0dffbed9149e6f00479cf43b since what it fixes is not a > > > regression in 4.10. >

> -----Original Message----- > From: Wood Scott-B07421 > Sent: Wednesday, July 03, 2013 5:32 PM > To: Yoder Stuart-B08248 > Cc: Alex Williamson; Alexander Graf; Wood Scott-B07421; Bhushan Bharat-R65777; Sethi Varun-B16395; > virtualization at lists.linux-foundation.org; Antonios Motakis; kvm at vger.kernel.org list; kvm- > ppc at vger.kernel.org; kvmarm at

> -----Original Message----- > From: Wood Scott-B07421 > Sent: Wednesday, July 03, 2013 5:32 PM > To: Yoder Stuart-B08248 > Cc: Alex Williamson; Alexander Graf; Wood Scott-B07421; Bhushan Bharat-R65777; Sethi Varun-B16395; > virtualization at lists.linux-foundation.org; Antonios Motakis; kvm at vger.kernel.org list; kvm- > ppc at vger.kernel.org; kvmarm at

Hi all, There''s a dead thread about this back at http://forums.sun.com/thread.jspa?threadID=5075157, but it would be really nice to have support for if/else control flow in actions. Reasons: 1. The ternary operator ?: is already there (though it doesn''t let you do anything with side effects) 2. The user can already write arbitrary and expensive non-cacheable predicates if

...is turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their guest DTs but neglect to add the often-overlooked "dma-coherent" property; as a result, we end up with the guest making non-cacheable accesses to the vring, the host doing so cacheably, both talking past each other and things going horribly wrong. We are working on a safer work-around. Fixes: c7070619f340 ("vring: Force use of DMA API for ARM-based systems with legacy devices") Reported-by: Robin Murphy <robin.murphy at arm.com> Cc: <stable at vger.kernel.org...

...is turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their guest DTs but neglect to add the often-overlooked "dma-coherent" property; as a result, we end up with the guest making non-cacheable accesses to the vring, the host doing so cacheably, both talking past each other and things going horribly wrong. We are working on a safer work-around. Fixes: c7070619f340 ("vring: Force use of DMA API for ARM-based systems with legacy devices") Reported-by: Robin Murphy <robin.murphy at arm.com> Cc: <stable at vger.kernel.org...

On 07/16/2013 04:51:12 PM, Yoder Stuart-B08248 wrote: > > > 3. VFIO_DEVICE_GET_REGION_INFO > > > > > > No changes needed, except perhaps adding a new flag. Freescale > > > has some > > > devices with regions that must be mapped cacheable. > > > > While I don't object to making the information available to the user > > just

Hi, Attached patch implements the VMCB cleanbits SVM feature. Upcoming AMD CPUs introduce them and they are basically hints for the CPU which vmcb values can be re-used from the previous VMRUN instruction. Each bit represents a certain set of fields in the VMCB. Setting a bit tells the cpu it can re-use the cached value from the previous VMRUN. Clearing a bit tells the cpu to reload the values

...is turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their guest DTs but neglect to add the often-overlooked "dma-coherent" property; as a result, we end up with the guest making non-cacheable accesses to the vring, the host doing so cacheably, both talking past each other and things going horribly wrong. To prevent regressing those existing use cases relying on implicit coherency, but still fixing the original problem of (coherent PCI) legacy devices behind IOMMUs, take the more conservative approach of only hitting the DMA API switch...

...is turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their guest DTs but neglect to add the often-overlooked "dma-coherent" property; as a result, we end up with the guest making non-cacheable accesses to the vring, the host doing so cacheably, both talking past each other and things going horribly wrong. To prevent regressing those existing use cases relying on implicit coherency, but still fixing the original problem of (coherent PCI) legacy devices behind IOMMUs, take the more conservative approach of only hitting the DMA API switch...

> -----Original Message----- > From: Wood Scott-B07421 > Sent: Tuesday, July 16, 2013 5:01 PM > To: Yoder Stuart-B08248 > Cc: Wood Scott-B07421; Alex Williamson; Alexander Graf; Bhushan Bharat-R65777; Sethi Varun-B16395; > virtualization at lists.linux-foundation.org; Antonios Motakis; kvm at vger.kernel.org list; kvm- > ppc at vger.kernel.org; kvmarm at lists.cs.columbia.edu

> -----Original Message----- > From: Wood Scott-B07421 > Sent: Tuesday, July 16, 2013 5:01 PM > To: Yoder Stuart-B08248 > Cc: Wood Scott-B07421; Alex Williamson; Alexander Graf; Bhushan Bharat-R65777; Sethi Varun-B16395; > virtualization at lists.linux-foundation.org; Antonios Motakis; kvm at vger.kernel.org list; kvm- > ppc at vger.kernel.org; kvmarm at lists.cs.columbia.edu

Hi I am using "caches_page :index" to cache a page. I delete this file via a cron tab command every 1 hour. However, right after the file is deleted the very next user experiences a huge delay because the page is being generated. Is there anyway to autogenerate the file before the very next user requests the page? A unix or ruby solution would do. thanks, -- nueromancer -- Posted