search for: cache_index

Displaying 7 results from an estimated 7 matches for "cache_index".

2020 Apr 28
0
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
...ges, register zero extension] Signed-off-by: Mike Stunes <mstunes at vmware.com> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> [ jroedel at suse.de: - Wrapped cache handling into vc_handle_cpuid_cached() - Used lower_32_bits() where applicable - Moved cache_index out of struct es_em_ctxt ] Co-developed-by: Joerg Roedel <jroedel at suse.de> Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/kernel/sev-es-shared.c | 12 ++-- arch/x86/kernel/sev-es.c | 119 +++++++++++++++++++++++++++++++- 2 files changed, 124 insertions(+), 7 d...
1998 Sep 04
0
Linux SMB Mount utils patch
...unsigned char *param, + int *lrdata, unsigned char **rdata, + int *lrparam, unsigned char **rparam); + +/* fs/smbfs/cache.c */ + +/* + * The cache index describes the pages mapped starting + * at offset PAGE_SIZE. We keep only a minimal amount + * of information here. + */ +struct cache_index { + unsigned short num_entries; + unsigned short space; + struct cache_block * block; +}; + +#define NINDEX (PAGE_SIZE-64)/sizeof(struct cache_index) +/* + * The cache head is mapped as the page at offset 0. + */ +struct cache_head { + int valid; + int status; /* error code or 0 */ + int entries;...
2020 May 06
0
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
...d-off-by: Mike Stunes <mstunes at vmware.com> >> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> >> [ jroedel at suse.de: - Wrapped cache handling into vc_handle_cpuid_cached() >> - Used lower_32_bits() where applicable >> - Moved cache_index out of struct es_em_ctxt ] >> Co-developed-by: Joerg Roedel <jroedel at suse.de> >> Signed-off-by: Joerg Roedel <jroedel at suse.de> >> --- >> arch/x86/kernel/sev-es-shared.c | 12 ++-- >> arch/x86/kernel/sev-es.c | 119 ++++++++++++++++++++++++++++++...
2020 May 20
2
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
...> > Signed-off-by: Mike Stunes <mstunes at vmware.com> > Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> > [ jroedel at suse.de: - Wrapped cache handling into vc_handle_cpuid_cached() > - Used lower_32_bits() where applicable > - Moved cache_index out of struct es_em_ctxt ] > Co-developed-by: Joerg Roedel <jroedel at suse.de> > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- ... > +struct sev_es_cpuid_cache_entry { > + unsigned long eax; > + unsigned long ebx; > + unsigned long ecx; > + unsigned l...
2020 May 20
2
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
...> > Signed-off-by: Mike Stunes <mstunes at vmware.com> > Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> > [ jroedel at suse.de: - Wrapped cache handling into vc_handle_cpuid_cached() > - Used lower_32_bits() where applicable > - Moved cache_index out of struct es_em_ctxt ] > Co-developed-by: Joerg Roedel <jroedel at suse.de> > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- ... > +struct sev_es_cpuid_cache_entry { > + unsigned long eax; > + unsigned long ebx; > + unsigned long ecx; > + unsigned l...
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by