Displaying 1 result from an estimated 1 matches for "cache_hint_desc".
2015 Mar 04
2
[LLVMdev] Mips patches for LLVM 3.5.2
...e, but it doesn't apply cleanly and would need some re-work that doesn't look trivial.
* r227430 - [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
o LLVM 3.5.2 doesn't have any of the test cases it modifies. I could merge the testcases too but I'm not aware of any downstream projects that need this fix.
Daniel Sanders
Leading Software Design Engineer, MIPS Processor IP
Im...