search for: c7e865e4

Displaying 3 results from an estimated 3 matches for "c7e865e4".

[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
2013 Sep 19
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you will have to compile with -O3. You can also invoke the MI (pre-RA) scheduler with llc option "-enable-misched". As you have pointed out, the post-isel scheduler is mandatory, and therefore you don't have to give any command line options. Currently, mips has only one generic scheduling itinerary model in
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
2013 Sep 19
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, LLVM, I found LLVM codegen has 3 passes for instruction scheduling: 1) pre-ra sched 2) post-ra sched 3) mi sched. for RISC machines, there are data hazard cases appear only after Register Allocation(RA). for example, $t0 is used immediately after writing(RAW): ld $t0, MEM add $t2, $t0, $0 There may be one or more stall in pipeline. Instruction scheduler can detect this kinds of conflict
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
2013 Sep 20
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
...ng list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130920/c7e865e4/attachment.html>