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618351
2013 Jan 12
1
[LLVMdev] Sub-Register Allocation
> LLVM's register coalescer and allocator don't try to reschedule
> instructions, which seems to be required here.
>
I think you're right. Looking at the instruction schedules before register
allocation, shows that it's scheduling the load before the zero move in one
case but not the other.
Is there an easy way I can trick the scheduler into putting these in the
right